ESD (Electrostatic Discharge) Simulation
Theory and Physics
What is ESD?
What exactly is being modeled in electrostatic discharge simulation? Is it that "zap" you feel?
Yes, exactly that "zap". However, humans only feel it above 3kV, but semiconductor ICs can be damaged at just a few hundred volts. Moreover, the ESD discharge pulse has a rise time of only 0.7 to 1 nanosecond, and the peak current reaches from a few amperes to tens of amperes. It's like a shockwave 1000 times faster than lightning causing dielectric breakdown across a path of just a few nanometers in the IC's oxide layer.
Wait, nanoseconds... Can simulation really reproduce such a fast phenomenon?
It can. For a 4kV ESD current in the Human Body Model (HBM), the peak reaches 7.5A with a 1ns rise time. ESD simulation analyzes the voltage and current distribution as this ultra-fast pulse propagates through PCB traces and reaches the IC's input protection circuit. To pass IEC 61000-4-2 Level 4 (±8kV contact discharge), it's necessary to optimize the ESD path impedance using 3D FEM.
In what specific scenarios is it used?
A typical example is the USB-C connector in a smartphone. When a user inserts a cable while charged, ESD current flows through the path: connector shell → GND plane → IC. If the impedance of this path is high, a voltage exceeding specifications appears between the IC's VSS-VDD pins, causing malfunctions or latch-up. Checking the current density map via simulation before shipping can prevent post-mass-production recalls.
ESD Test Models (HBM, MM, CDM, IEC)
I've heard there are various models like HBM and IEC. How are they different?
There are multiple ESD test models depending on the target level. Their circuit constants differ, so the shape of the current waveform is completely different.
| Model | Standard | C [pF] | R [Ω] | Rise Time | Target Level |
|---|---|---|---|---|---|
| HBM | ANSI/ESDA/JEDEC JS-001 | 100 | 1,500 | 2–10 ns | Device (IC Chip) |
| MM | EIAJ ED-4701 | 200 | 0 (effectively <10) | <1 ns | Device (Oscillatory Waveform) |
| CDM | ANSI/ESDA/JEDEC JS-002 | Device Dependent | — | 100–400 ps | Device (Mounted State) |
| IEC | IEC 61000-4-2 | 150 | 330 | 0.7–1 ns | System (Entire Product) |
A 100 picosecond rise time for CDM... That sounds incredibly difficult to reproduce in simulation.
Exactly. CDM requires a time step on the order of picoseconds, making the computational cost orders of magnitude higher. Therefore, in practice, a two-step approach is common: first, perform pass/fail judgment at the system level using the IEC model, and if it fails, then analyze the IC's input protection circuit in detail using the HBM model.
Governing Equations
What are the "foundational" equations for ESD analysis?
The basics are Maxwell's equations. Since the ESD pulse has frequency components spanning from DC to several GHz, the quasi-static approximation cannot be used. Full-wave analysis is required.
Maxwell's Equations (Time Domain)
$$\nabla \times \mathbf{E} = -\frac{\partial \mathbf{B}}{\partial t}$$ $$\nabla \times \mathbf{H} = \mathbf{J} + \frac{\partial \mathbf{D}}{\partial t}$$ $$\nabla \cdot \mathbf{D} = \rho_v$$ $$\nabla \cdot \mathbf{B} = 0$$For ESD, the displacement current term $\partial \mathbf{D}/\partial t$ is particularly important. Because the $di/dt$ of an ESD pulse reaches several GA/s, the magnetic field variation is also intense, scattering noise as EMI (electromagnetic interference) to surrounding circuits. To accurately track this "scattering," Maxwell's equations must be solved without omission.
Mathematical Model of HBM Current Waveform
What mathematical formula represents the HBM waveform?
The HBM equivalent circuit is an RC model discharging a 100pF capacitor through a 1.5kΩ resistor. However, because the discharge path has parasitic inductance $L_p$, the actual waveform becomes a double exponential function.
HBM Current Waveform (Double Exponential Function Model)
$$i_{\text{HBM}}(t) = \frac{I_p}{1 - k}\left(e^{-t/\tau_1} - e^{-t/\tau_2}\right)$$Where:
- $I_p$: Peak current [A] (approx. 2.67A for 4kV HBM)
- $\tau_1 = RC = 150\,\text{ns}$: Decay time constant
- $\tau_2 = L_p / R \approx 2\text{--}10\,\text{ns}$: Rise time constant
- $k = \tau_2 / \tau_1$: Time constant ratio
Because the difference between $\tau_1$ and $\tau_2$ is large, it rises sharply and decays slowly, right?
Exactly. Also, the energy stored by ESD is important.
ESD Stored Energy
$$E_{\text{ESD}} = \frac{1}{2}CV^2$$For example, for the IEC model ($C = 150\,\text{pF}$, $V = 8\,\text{kV}$):
$$E_{\text{ESD}} = \frac{1}{2} \times 150 \times 10^{-12} \times (8000)^2 = 4.8\,\text{mJ}$$4.8mJ may seem tiny, but when released in nanoseconds, the instantaneous power reaches several kilowatts. Whether the IC's input protection circuit (ESD clamp) can safely absorb this energy is the key design challenge.
IEC 61000-4-2 Current Source Model
How does the IEC waveform differ from HBM?
The IEC 61000-4-2 waveform has a unique shape with two peaks: an initial sharp spike and a subsequent broad hump. The standard defines this waveform with four parameters.
| Parameter | Level 4 (±8kV Contact) | Tolerance |
|---|---|---|
| Initial Peak Current $I_1$ | 30 A | ±15% |
| Current at $t = 30\,\text{ns}$ $I_2$ | 16 A | ±30% |
| Current at $t = 60\,\text{ns}$ $I_3$ | 8 A | ±30% |
| Rise Time $t_r$ | 0.7–1 ns | — |
30A initial peak at 8kV! That's about 10 times HBM, isn't it?
Yes. IEC is a system-level test, simulating the entire realistic discharge path: human hand → enclosure → PCB → IC. In simulation, this waveform is injected as a current source at the discharge point, and the response on the PCB is analyzed. As an equivalent circuit, it can be approximated by a two-stage RLC circuit like the following.
IEC Waveform Equivalent Circuit Approximation
$$i_{\text{IEC}}(t) = I_1 \cdot A_1 \cdot e^{-t/\tau_a}\sin(\omega_1 t) + I_2 \cdot A_2 \cdot \left(e^{-t/\tau_b} - e^{-t/\tau_c}\right)$$First term: Initial spike ($\tau_a \approx 2\,\text{ns}$, $\omega_1$ depends on parasitic L)
Second term: Broad hump ($\tau_b \approx 20\,\text{ns}$, $\tau_c \approx 2\,\text{ns}$)
Physics of Ground Bounce
I often hear about ground bounce. Why is it a problem with ESD?
The ground plane is not a "perfect zero-potential plane." In reality, the plane also has inductance $L_{\text{gnd}}$. When ESD current flows, this inductance causes a localized potential rise. This is ground bounce.
Ground Bounce Voltage
$$V_{\text{bounce}} = L_{\text{gnd}} \cdot \frac{di}{dt}$$Estimating $di/dt$ for the IEC Level 4 initial spike:
$$\frac{di}{dt} \approx \frac{30\,\text{A}}{1\,\text{ns}} = 30 \times 10^9\,\text{A/s} = 30\,\text{GA/s}$$If $L_{\text{gnd}} = 1\,\text{nH}$ (about one via's worth):
$$V_{\text{bounce}} = 1 \times 10^{-9} \times 30 \times 10^9 = 30\,\text{V}$$30V from just one via!? The ground can fluctuate that much...?
That's why in ESD countermeasures, it's a golden rule to place multiple GND vias immediately adjacent to the discharge point to lower $L_{\text{gnd}}$. For example, placing four vias in parallel reduces $L_{\text{gnd}}$ to about 1/4, lowering the bounce voltage to 7.5V. In simulation, a common practice is to visualize the ground plane's potential distribution with a color map to identify "hot spots" with large bounce.
TVS Clamp Voltage Model
What is the "clamp voltage" of a TVS diode? It always comes up in ESD countermeasures.
TVS (Transient Voltage Suppressor) is a protection device that absorbs ESD current. Normally, it has high impedance and doesn't affect the signal, but when ESD is applied, it breaks down to low impedance and "clamps" the voltage to a certain value.
TVS Clamp Voltage Relation
$$V_{\text{clamp}} = V_{\text{BR}} + I_{\text{ESD}} \cdot R_{\text{dyn}}$$Where:
- $V_{\text{BR}}$: Breakdown voltage (TVS design value, e.g., 6.4V typ. for a 5V part)
- $R_{\text{dyn}}$: Dynamic resistance (approx. 0.1–2Ω. Lower is higher performance)
- $I_{\text{ESD}}$: ESD current flowing through the TVS [A]
Example: For $V_{\text{BR}} = 6.4\,\text{V}$, $R_{\text{dyn}} = 0.5\,\Omega$, $I_{\text{ESD}} = 16\,\text{A}$
$$V_{\text{clamp}} = 6.4 + 16 \times 0.5 = 14.4\,\text{V}$$If the IC's absolute maximum rating is, say, 7V, then 14.4V would be a failure, right...?
That is precisely the core of ESD simulation. If the clamp voltage is too high, you either change to a TVS with a smaller $R_{\text{dyn}}$, or move the TVS closer to the discharge point to reduce the voltage increase due to trace inductance. In simulation, the standard approach is to couple the TVS's SPICE model with 3D electromagnetic field analysis to calculate the effective clamp voltage at the IC pin.
Another important factor is the effect of the trace inductance $L_{\text{trace}}$ between the TVS and the IC pin.
Effective Voltage at IC Pin
$$V_{\text{IC}} = V_{\text{clamp}} + L_{\text{trace}} \cdot \frac{di}{dt}$$For $L_{\text{trace}} = 2\,\text{nH}$ (approx. 3mm trace), $di/dt = 30\,\text{GA/s}$:
$$V_{\text{IC}} = 14.4 + 2 \times 10^{-9} \times 30 \times 10^9 = 14.4 + 60 = 74.4\,\text{V}$$74V!? A mere 3mm trace adds 60V!?
That's why in the world of ESD countermeasures, the golden rule is "Place the TVS next to the IC, even 1mm closer matters." At this point, just looking at the schematic connections isn't enough for countermeasures. You can see why 3D electromagnetic field analysis of the PCB layout becomes essential, right?
ESD Discharge Time is 1 Nanosecond—A Shock 1000 Times Faster Than Lightning
The static electricity you feel when touching a doorknob in winter is about 3–5kV. The discharge lasts only a few nanoseconds, about 1/1000th of a lightning discharge (a few microseconds). In the 1960s, IBM engineers investigated the cause of a sudden increase in defect rates at semiconductor factories during winter and identified static electricity as the cause. This led to the creation of the Human Body Model (HBM)—modeling the human body as a 100pF capacitor and a 1.5kΩ resistor—a standard still in use today. If the human body's capacitance were larger, ESD countermeasure costs would have skyrocketed.
Physical Meaning of Each Term
- HBM Double Exponential First Term $e^{-t/\tau_1}$: Represents the RC discharge decay. $\tau_1 = RC = 100\,\text{pF} \times 1.5\,\text{k}\Omega = 150\,\text{ns}$ determines the "tail" length of the discharge pulse. A shorter time constant means faster energy release, increasing thermal stress on the IC.
- HBM Double Exponential Second Term $e^{-t/\tau_2}$: Represents the rise due to parasitic inductance $L_p$ in the discharge path. $\tau_2 = L_p / R$; smaller $L_p$ results in a steeper rise. For CDM, $L_p$ is extremely small, leading to ultra-fast rise times in the 100ps range.
- Ground Bounce $V = L \cdot di/dt$: The circuit version of Faraday's law of electromagnetic induction. It's the back electromotive force due to self-inductance. Because ESD current's $di/dt$ reaches tens of GA/s, even a few nH of inductance generates tens of volts.
- TVS Dynamic Resistance $R_{\text{dyn}}$: The differential resistance in the breakdown region of the TVS's I-V characteristic. Can be back-calculated from the datasheet's "Clamp voltage at $I_{pp}$". Small-signal TVS often have larger $R_{\text{dyn}}$, which can lead to excessive clamp voltage under high-current ESD.
Assumptions and Applicability Limits
- HBM/IEC waveform models use lumped parameter approximation: Valid when the discharge path length is sufficiently shorter than the ESD waveform's wavelength ($c / f_{\text{max}} \approx 0.1\,\text{m}$). For large PCBs, a distributed parameter model is needed.
- TVS dynamic resistance $R_{\text{dyn}}$ uses steady-state approximation: In reality, there is a turn-on delay (0.5–1ns) in the nanosecond region, during which the TVS has high impedance. Overshoot during this delay can sometimes be problematic.
- GND plane inductance estimation uses DC approximation: At GHz frequencies, skin effect and resonance modes become significant, making the simple $L \cdot di/dt$ insufficient. Full-wave 3D analysis is required.
- Linear medium assumption: Arc discharge plasma generation is a nonlinear phenomenon, requiring additional models near the discharge gap.
Dimensional Analysis and Unit Systems
| Physical Quantity | SI Unit | ESD-Specific Notes |
|---|---|---|
| ESD Voltage | V | Often expressed in kV. 8kV = 8000V. Beware of input errors. |
| Peak Current | A | 30A for IEC 8kV. 2.67A for HBM 4kV. |
| Rise Time | s | Expressed in ns. 1ns = 10⁻⁹s. Frequency conversion $f \approx 0.35/t_r$. |
| Parasitic L | H | Expressed in nH. One PCB via ≈ 0.5–1nH. |
| Parasitic C | F | Expressed in pF. TVS parasitic capacitance is 0.1–a few pF (problematic for high-speed signals). |
| $di/dt$ | A/s | Expressed in GA/s. Around 30GA/s for IEC initial spike. |
Numerical Methods and Implementation
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