Impedance Matching (SI) — Termination Design, Reflection Suppression, and DDR5 ODT

That's correct if we're only talking about DC (direct current). But in the world of SI (Signal Integrity), signals have broadband components from DC to the Nyquist frequency. For example, a 28 Gbps NRZ signal requires managing a bandwidth up to 14 GHz, and a 56 Gbps PAM4 signal requires managing up to 14 GHz (baud rate 28 Gbaud).

It does change. The characteristic impedance of a PCB fluctuates due to increased conductor resistance from the skin effect and frequency dispersion of the substrate dielectric's permittivity (changes in Dk, Df). At low frequencies, $Z_0$ appears larger, approaching the nominal value at high frequencies. Furthermore, the input/output impedance of drivers and receivers is also frequency-dependent. That's why "managing matching across the entire bandwidth" is the essence of SI.

When there is a mismatch, a portion of the signal reflects back to the source. This back-and-forth movement causes ringing and overshoot in the waveform at the receiver side, closing the eye pattern. For example, in PCIe Gen5 (32 GT/s), 1 UI is only about 31 ps. Even a reflection of just a few percent can worsen jitter or ISI (Inter-Symbol Interference) within that time frame.

It's measured by the reflection coefficient $\Gamma$ (Gamma). It is defined from the transmission line's characteristic impedance $Z_0$ and the load impedance $Z_L$ as follows.

$\Gamma = 0$ means perfect matching (zero reflection), $\Gamma = +1$ is an open end (full reflection, in-phase), $\Gamma = -1$ is a shorted end (full reflection, out-of-phase). In SI, a general target is $|\Gamma| < 0.1$ (return loss $-20\log_{10}|\Gamma| > 20$ dB).

VSWR (Voltage Standing Wave Ratio) is another scale representing the reflection coefficient.

Perfect matching gives $\text{VSWR} = 1$, full reflection gives $\text{VSWR} \to \infty$. VSWR is often used in the RF/microwave world, but in SI, the dB notation of $S_{11}$ (return loss) is more common. Both are ultimately transformed representations of $\Gamma$.

The general characteristic impedance of a transmission line is described by the distributed circuit RLGC parameters.

Here, $R(f)$ is the conductor resistance increasing proportionally to $\sqrt{f}$ due to the skin effect, $L(f)$ is the per-unit-length inductance where internal inductance decreases at high frequencies, $G(f)$ is the conductance dependent on dielectric loss, and $C(f)$ is the per-unit-length capacitance fluctuating due to permittivity dispersion.

Exactly. In the high-frequency limit, $R \ll \omega L$, $G \ll \omega C$, so $Z_0 \approx \sqrt{L/C}$ converges. This is the so-called "nominal 50Ω". But below 100 MHz, the $R$ term cannot be ignored, and the impedance fluctuates considerably. This is why, even for something like DDR5 where the clock frequency is a few GHz, you must consider the entire signal bandwidth (DC to Nyquist).

Of course. To match a complex impedance (a load with a reactive component), L-type, T-type, or π-type matching networks are needed. For an L-type network, to match a source impedance $Z_S = R_S$ and a load $Z_L = R_L + jX_L$, the shunt and series reactances are designed according to the following condition.

Here $R_{\text{high}}$ is the larger of $R_S, R_L$, and $R_{\text{low}}$ is the smaller one. Once $Q$ is determined, the shunt element reactance $X_P = R_{\text{high}} / Q$ and the series element reactance $X_S = Q \cdot R_{\text{low}}$ can be designed. However, this is matching at a single frequency; for broadband matching, multi-section stepped matching is required.

There are Binomial matching and Chebyshev matching using cascaded quarter-wave transformers. The return loss bandwidth of an N-section matcher widens according to the number of sections. In digital SI, absorption-type matching using termination resistors is more mainstream than pure LC matching, but impedance step-change designs are used in transition parts like connectors and packages.

It's used a ton. When S-parameters are measured with a VNA (Vector Network Analyzer), $S_{11}$ (return loss) is plotted on the Smith Chart. At that time, by looking at how far the impedance trajectory along the frequency sweep deviates from the center of the circle (the perfect match point), the quality of the match can be understood at a glance.

For example, if you look at the $S_{dd11}$ of a differential pair on a Smith Chart and it deviates inductively (upper half of the chart) in the low-frequency region, it can be corrected with a series capacitor. If it deviates capacitively at high frequencies, you need to reduce the parasitic capacitance of the pad. This kind of intuitive judgment is the strength of the Smith Chart.

The most commonly used is series termination (source termination). A resistor $R_s$ is inserted in series at the driver's output. The sum of this and the driver's output impedance $Z_{out}$ is made to match the transmission line's $Z_0$.

For example, if $Z_0 = 50\,\Omega$ and the driver's $Z_{out} = 17\,\Omega$, then insert $R_s = 33\,\Omega$. The signal from the driver is divided by $R_s$ and $Z_0$, so the initial voltage traveling on the transmission line becomes $V_{DD}/2$. It then fully reflects at the receiver end (open end) and returns to $V_{DD}$.

Yes, it only reaches full amplitude when the reflected wave returns. In other words, it takes twice the round-trip delay (2 $T_d$) for the signal to settle. This is not a problem for short traces, but delay becomes a concern for long traces. Conversely, the advantage is low power consumption. Because almost no DC current flows. This source termination is standard for DDR4/5 clock lines and command lines.

Use parallel termination, where a resistor equal to $Z_0$ is connected to ground or the power supply at the receiver end (load side). The incident wave is absorbed the moment it arrives at the receiver, so reflection becomes almost zero. Full amplitude is obtained in a one-way delay.

Because DC current flows constantly, leading to high power consumption. Applying 3.3V across 50Ω draws 66 mA, consuming 220 mW. If there are 32 data lines on a bus, the total is 7 W. This is fatal for mobile devices. Therefore, source termination is used for point-to-point wiring, and parallel termination is used for bus-type (1:N) configurations.

That's where AC termination (RC termination) comes in. A resistor $R$ and a capacitor $C$ are connected in series to ground at the receiver end. For high-frequency components (signal edges), $R$ provides matching and absorbs reflection, while for DC, the capacitor blocks it, so no steady-state current flows.

The design point is to make the RC time constant $\tau = RC$ sufficiently larger than the signal's bit period. Generally, $C = 30\text{–}100$ pF, $R = Z_0 = 50\,\Omega$. The weakness of AC termination is that for burst signals or random patterns, the capacitor's charging voltage may drift, causing the DC bias to shift. It is more often used for low-to-medium speed parallel buses than for memory buses.

This method connects two resistors ($R_1$ to $V_{DD}$ and $R_2$ to GND) at the receiver end to simultaneously achieve an equivalent $Z_0$ parallel termination and a DC bias. The Thevenin equivalent impedance is $R_1 \parallel R_2 = R_1 R_2 / (R_1 + R_2)$, and the Thevenin equivalent voltage is $V_{TH} = V_{DD} \cdot R_2 / (R_1 + R_2)$. Used in cases like GTL+ buses or LVDS where bus-level bias is required.

ODT (On-Die Termination) is a technology that integrates programmable termination resistors inside the memory chip die. It was first introduced in DDR3 and has evolved with each generation. Since external termination resistors become unnecessary, the stub length (wiring between the package pin and the termination resistor) becomes almost zero, significantly suppressing reflections at high frequencies.