PCB Signal Integrity Evaluation Using TDR Analysis
Theoretical Foundations of TDR Analysis for PCB Signal Integrity Evaluation
What is TDR?
Professor, what kinds of problems can TDR detect in PCBs? I was told to "get TDR" at work, but I'm not sure what to look for...
In a nutshell, TDR is "radar for PCBs." You send a fast step signal down the trace and observe what reflects back and when. The reflected waveform reveals all sorts of problems: via impedance discontinuities, connector parasitic capacitance, trace width variations, reference plane defects—they all show up as steps in the waveform.
Radar and the same principle? But why use TDR instead of taking S-parameters with a VNA? What's the difference?
Great question. VNA S-parameters are in the frequency domain and show the overall behavior of the entire path. But TDR is time-domain, so you can see exactly where the problem is. For instance, if a via 30mm from the connector has impedance jump, TDR makes that instantly obvious. In practical SI work, we use both—but TDR is unbeatable for spatial localization of problems.
I see—TDR's strength is locating problems in space. What kind of signal do we actually inject?
A TDR instrument generates a step function (rise time roughly 20–35 ps). This step propagates down the transmission line. Whenever impedance changes, some energy reflects backward. The reflection coefficient is:
Here $Z_0$ is the system reference impedance (typically 50 $\Omega$) and $Z_L$ is the local impedance at the discontinuity. If $\rho > 0$, impedance rose (inductive discontinuity). If $\rho < 0$, impedance dropped (capacitive discontinuity).
Reflection Coefficient and Impedance Profile
So once we know the reflection coefficient, we can calculate the actual trace impedance?
Exactly. From the measured reflection coefficient $\rho(t)$ at time $t$, the local impedance is:
Plot this across time and you get the impedance profile. SI engineers look at this and say things like "This is 50 $\Omega$ here but jumps to 55 $\Omega$ at the via" or "Drops to 45 $\Omega$ at the connector." For DDR5 memory designs, the specification is typically $\pm 5\%$ (47.5–52.5 $\Omega$).
Wow! So the waveform alone gives us a kind of "health check" for the trace. But how do we get position from time-domain data?
Spatial Resolution and Rise Time
The conversion from time to position is straightforward. The signal makes a round trip, so:
where $v_p$ is the propagation velocity in the transmission line. In FR-4 substrates ($\varepsilon_r \approx 4.0$), this is roughly $v_p \approx 1.5 \times 10^8$ m/s (about half the speed of light). The TDR instrument's rise time $t_r$ determines spatial resolution:
For instance, with $t_r = 20$ ps, you get $\Delta x_{\min} \approx 1.5$ mm. Discontinuities shorter than 1.5 mm won't separate in the waveform. For DDR5 and PCIe Gen5/6 designs, you need TDR equipment with rise times below 20 ps.
Got it—shorter rise time means finer spatial detail. What kind of discontinuities typically show up in real PCBs?
TDR Signatures of Discontinuities
In the field, these four are the most common:
| Discontinuity | TDR Waveform Feature | Physical Cause | Typical Impact |
|---|---|---|---|
| Via (through/blind) | Capacitive dip (downward step) | Stub capacitance, pad capacitance | 50→42 $\Omega$ drop |
| Connector interface | Inductive spike + capacitive dip combo | Pin inductance, parasitic capacitance | $\pm$10 $\Omega$ swing |
| Trace width variation | Gradual impedance shift | Etching variation, prepreg thickness change | $\pm$3–5 $\Omega$ |
| GND plane cutout | Large inductive step (upward) | Return path disruption | 50→70 $\Omega$ or higher |
Ah, so vias show as capacitive (down) and ground plane cutouts as inductive (up). You can tell the cause just by the direction?
Exactly. $\rho > 0$ (wave jumps up) means impedance increased—inductive discontinuity. $\rho < 0$ (drops down) means impedance decreased—capacitive discontinuity. Keep this in mind and your TDR waveform interpretation speed multiplies.
TDR: The "PCB Version" of Radar—Same Physics, Different Scale
TDR (Time Domain Reflectometry) is fundamentally the same as aircraft radar. Send a pulse, wait for the reflection, measure the round-trip time to locate the target. The difference is scale—radar measures hundreds of kilometers in microseconds; TDR measures centimeters in picoseconds. TDR originally came from power utilities (locating cable breaks), then got adapted for GHz-band high-speed digital where it became the "X-ray" for PCB traces. A 50 $\Omega$ straight line should look perfectly flat on TDR; if it doesn't, something's hiding in there that needs to be found.
Numerical Computation Methods for TDR Analysis of PCB Signal Integrity
Simulated TDR Extraction Methods
Can you also generate TDR waveforms from simulation, not just measurement?
Absolutely. Overlaying measured and simulated TDR and verifying that your FEM model is correct—this is the core SI workflow. There are two main approaches:
- Direct method (time domain): Feed a step signal into FDTD or FIT and observe reflections directly. CST Studio is strong here.
- Indirect method (frequency→time): Run FEM to get S-parameters ($S_{11}$) over frequency, then inverse FFT to TDR waveform. HFSS/SIwave typically use this approach.
The indirect route dominates in practice because frequency-domain meshing is lighter and you can reuse existing S-parameter data.
How exactly do you turn S-parameters into a TDR waveform?
If you have $S_{11}(f)$, here's the recipe:
- Multiply $S_{11}(f)$ by the step function spectrum $V_{\text{step}}(f) = 1/(j2\pi f)$
- Apply inverse FFT to get the time-domain reflected waveform $v_{\text{refl}}(t)$
- Superpose the incident step: $V_{\text{TDR}}(t) = V_0 + v_{\text{refl}}(t)$
- Convert to impedance: $Z(t) = Z_0 \cdot V_{\text{TDR}}(t) / (2V_0 - V_{\text{TDR}}(t))$
The frequency range limits resolution. For instance, $f_{\max} = 20$ GHz gives an effective rise time of about $0.35/f_{\max} \approx 17.5$ ps.
Transmission Line Modeling
Is there an alternative to full 3D simulation? Solving the entire board in 3D sounds expensive...
Practical SI work uses a layered approach. Transmission line modeling comes in three tiers:
| Method | Application | Accuracy | Cost | Typical Tools |
|---|---|---|---|---|
| 2D cross-section | Extract trace RLGC parameters | High for traces | Seconds–minutes | SIwave, Polar Si9000 |
| 2.5D (MoM/BEM) | Package, via arrays | Medium–high | Minutes–hours | SIwave, Momentum |
| 3D full-wave | Connectors, complex via structures | Highest | Hours–days | HFSS, CST |
The real-world flow is: extract RLGC from 2D, solve vias and connectors in 3D, assemble everything in a circuit simulator, generate TDR. Doing all 3D is usually wasteful.
Full-Wave Analysis vs. Circuit Extraction
What's the difference between full-wave and circuit model extraction? Which should I trust?
Full-wave (FEM/FDTD/MoM) solves Maxwell's equations directly—theoretically most accurate. But results depend on mesh quality, port setup, and material accuracy. Circuit extraction converts full-wave results into RLC equivalent circuits. Advantages:
- SPICE simulators (HSpice, ADS) run transient analysis much faster
- Combine with driver/receiver IBIS models for system-level TDR and eye diagram
- Parametric studies (trace length, termination tweaks) run instantly
One caveat: a circuit model is only valid within the frequency range of the underlying full-wave analysis. Taking a 20 GHz model and using it for 56 Gbaud NRZ is dangerous.
Practical Application of TDR Analysis for PCB Signal Integrity Evaluation
TDR Measurement Setup
What equipment and prep do I need for hands-on TDR measurement?
Here's what you need:
| Item | Specification Example | Notes |
|---|---|---|
| TDR-capable oscilloscope | Keysight DCA-X 86100D / Tektronix DSA8300 | Bandwidth 50–70 GHz, rise time 20–35 ps |
| Probe or SMA cable | Phase-stable semi-rigid cable | Minimize ground lead length |
| Calibration substrate | Open/Short/Load/Thru (OSLT) | Define measurement plane via OSLT calibration |
| Test board SMA pad | SMA connector pad at DUT input | Better reproducibility than probing |
Calibration is needed, like with VNA, right? Where do you calibrate to?
Ideally all the way to the DUT input—the SMA connector tip. This is "connector-tip calibration." Poor calibration lets the connector's own impedance variation leak into the DUT measurement. That's why production test boards have SMA pads at the measurement point. Freehand probing has long ground leads that inject spurious inductance, making it hard to distinguish real impedance from probe artifacts.
Model Correlation
I keep hearing "correlation." What exactly does that mean? Just overlay the waveforms?
Overlaying is the first step. Here's the full correlation workflow:
- Acquire measured TDR—use calibrated equipment to record impedance profile
- Generate simulated TDR—compute S-parameters from the 3D model, IFFT to TDR
- Align time axes—match measurement planes. Adjust delays until electrical lengths agree
- Compare waveforms—impedance absolute difference should be $\pm 2.5\,\Omega$ (within $\pm 5\%$ of 50 $\Omega$)
- Adjust model parameters—primary tuning knobs are:
| Parameter | Affects TDR | Tuning Strategy |
|---|---|---|
| Substrate $\varepsilon_r$ | Overall impedance level and delay | Adjust Dk from datasheet by $\pm 5\%$ |
| Conductor surface roughness (Rz) | Loss-induced waveform slope | Huray/Hammerstad-Jensen model tuning |
| Via geometry (pad, antipad, stub) | Capacitive dip at via | Incorporate manufacturing tolerances |
Once correlation is good, is the model "reliable"?
Yes—a validated model becomes a trustworthy tool. You can then simulate design changes (more vias, layer swaps, trace routing) without building prototypes every time. This compresses design cycles dramatically. That's the whole point of V&V (Verification & Validation).
Time-Gating and De-Embedding
What's "time-gating"? A technique to boost measurement accuracy?
Time-gating is "carving out" a specific time window from the TDR waveform. Example: you measure connector→trace→via→trace→connector. To extract just the trace-and-via impedance (the DUT), you mask off the connector sections with a time window. This removes connector artifacts from the measurement.
I've also heard "de-embedding." Is that different from time-gating?
Similar but more rigorous. Time-gating is an approximate filtering approach; de-embedding is a mathematical technique. You measure the test fixture (connector + pads + short trace) S-parameters separately, then mathematically remove them from the total measurement:
This gives cleaner DUT isolation. For 56 Gbaud PAM4 and higher, de-embedding becomes essential—time-gating alone loses too much accuracy.
Practical Checklist
What should I absolutely check when running TDR in production?
- Before measurement: OSLT calibration, cable phase stability, board temperature stabilization
- During measurement: Dual-channel simultaneous capture for differential pairs, multiple runs for repeatability
- Simulation side: Confirm substrate stackup info, account for via back-drill, apply surface roughness model
- Correlation: Reference plane alignment, impedance error $\leq \pm 5\%$, delay error $\leq \pm 3\%$
- Pass/fail criteria: Use specification targets (DDR5: 40 $\Omega$ diff / PCIe: 85 $\Omega$ diff / USB4: 85 $\Omega$ diff $\pm 10\%$)
TDR Probe Ground Lead Length Destroys Measurement Accuracy
A common pitfall: even a 10 mm ground lead on your TDR probe can inject enough inductance to create spurious steps in the waveform, making it impossible to tell whether the feature is real or just probe artifact. Production setups use SMA pads on the board with direct coaxial connection, or specialized low-inductance probes. The "measurement fixture design" is actually part of the SI analysis—don't shortcut it.
PCB Signal Integrity Evaluation Using TDR: Software & Solver Comparison for TDR Analysis of PCB Signal Integrity
TDR Measurement Instruments
What measurement gear exists for TDR?
| Vendor | Key Product | Bandwidth | Rise Time | Remarks |
|---|---|---|---|---|
| Keysight | DCA-X 86100D + 54754A TDR module | 70 GHz | 17 ps | SI industry standard. IConnect integration |
| Tektronix | DSA8300 + 80E10B module | 50 GHz | 20 ps | Dual differential TDR/TDT. IConnect compatible |
| Picotest | Bode 100 + TDR option | 10 GHz | 50 ps | Low-cost. PDN analysis integration |
For high-speed (>25 Gbps), Keysight or Tektronix is virtually mandatory. Modern oscilloscopes integrate SI software to display TDR and eye patterns simultaneously.
SI Simulation Tools
What tools on the simulation side support TDR analysis?
| Tool | Developer | Method | TDR Support | Strength |
|---|---|---|---|---|
| Ansys HFSS | Ansys Inc. | FEM (3D) | S-parameter to IFFT conversion | High-accuracy connector/package analysis |
| Ansys SIwave | Ansys Inc. | MoM/BEM (2.5D) | Direct TDR output | Fast PCB trace analysis. HFSS integration |
| CST Studio Suite | Dassault Systemes | FIT/FDTD (3D) | Direct time-domain calculation | Strong time-domain solver. EMC evaluation |
| Keysight ADS | Keysight | Circuit + MoM | Transient analysis | Measurement data integration. IBIS support |
| Cadence Sigrity | Cadence | FEM + MoM | PowerSI/Clarity 3D support | EDA tight integration. CAD-driven analysis |
| Polar Si9000e | Polar Instruments | 2D cross-section | Design impedance calculation | Stackup design industry standard |
Which one should I choose on a budget?
Depends on your role:
- Stackup design phase → Polar Si9000e
- Full PCB TDR after layout → SIwave / Sigrity
- High-precision connector/package work → HFSS / CST
- Measurement–simulation correlation → ADS (works best with Keysight gear)
- System-level channel simulation → ADS / Sigrity SystemSI
Most SI teams run a 2D + 3D + circuit simulator combo.
Keysight IConnect Hidden Power—Auto-Extract RLGC from Measured TDR
Keysight IConnect (formerly TDA Systems) is the specialized CAD-SI integration platform. Its killer feature: automatically reverse-calculate RLGC transmission-line parameters from measured TDR data. The differential pair T-LINE auto-extraction lets you automate the production TDR→SPICE model flow. Measured TDR→RLGC extraction→SPICE model→channel simulation all in one tool. A huge efficiency gain for correlation work.
Advanced Research in TDR Analysis for PCB Signal Integrity
Latest Trends
How is TDR evolving for future ultra-high-speed designs like 112 Gbps PAM4?
TDR technology is advancing alongside bandwidth. Latest trends:
- 112G PAM4 TDR: Sub-10 ps rise-time modules now available. Spatial resolution below 0.7 mm allows microvia detection under BGAs
- Machine learning for TDR analysis: CNN/LSTM models for automatic good/bad waveform classification in production testing
- Frequency-dependent loss in TDR: Moving beyond lossless approximation. Loss-corrected TDR accounts for dielectric and conductor loss frequency dependence
- Automated 3D-to-TDR correlation: Genetic algorithms and Bayesian optimization to auto-tune material parameters, matching simulation to measurement
- Co-Packaged Optics (CPO): TDR evaluates electrical-to-optical boundary impedance matching in integrated packages
Cool—but won't ML replace engineer judgment eventually?
ML is superb at pattern detection but cannot explain "why." When a TDR shows a capacitive dip, a physics-literate engineer can pinpoint "via stub too long" or "antipad diameter off spec." Only deep understanding of the Telegraph equation and reflection physics lets you diagnose and fix root causes. Use ML as a helper, not a replacement.
PCB Signal Integrity Evaluation Using TDR: Common Issues & Debugging TDR Analysis for PCB Signal Integrity Evaluation
Common Pitfalls and Solutions
What are beginner mistakes I should know upfront?
| Symptom | Cause | Fix |
|---|---|---|
| TDR doesn't start at 50 $\Omega$ | Missing or bad calibration | Redo OSLT. Check cal substrate contact |
| Measured vs. simulated waveform timing mismatches | Reference plane mismatch | Verify port position. Compensate electrical length |
| Overall impedance too high/low | Substrate Dk off-spec | Adjust Dk $\pm 5\%$ from datasheet |
| Via dip deeper than simulation predicts | Via stub longer than modeled (insufficient back-drill) | Cross-section analysis. Check actual stub length |
| Differential TDR modes won't separate | Differential probe deskew not done | Run differential calibration and deskew |
| Ringing in TDR waveform | TDR probe ground lead too long | Use SMA direct connection or low-inductance probe |
| Simulated loss doesn't match measured | Surface roughness model not applied | Use Huray model. Adjust Rz parameter (2–5 μm) |
Looks like calibration and Dk are the big ones. And "back-drill"—what's that?
Back-drilling removes the unused stub portion of through-hole vias in multilayer boards. Without it, the stub acts as a short transmission line stub that resonates at high frequency, creating extra reflection on TDR. The rule: keep stub length below 0.2 mm. If your actual stackup has longer stubs, your simulation must model them—compare cross-section photos to verify.
TDR makes way more sense now! Measurement setup, correlation, time-gating—it all connects. Ready to try it on our designs.
That's the spirit! Go measure your board, compare to simulation, and learn from the gaps. The physical waveform never lies—it teaches faster than any textbook. Keep me posted on what you find.
Related Topics
Explore interactive simulators to deepen your understanding of this topic
Simulator ListRelated Fields
Detail
Error