› Semiconductor CMP Wafer Pad Pressure Uniformity Simulator Back
Semiconductor CMP

Semiconductor CMP Wafer Pad Pressure Uniformity Simulator

Evaluate chemical-mechanical planarization (CMP) recipes for 200/300/450mm wafers with the Preston equation. Adjust load, RPM, retainer-ring pressure, slurry flow and process (SiO2/W/Cu/Co) and watch the average pressure, relative velocity, Preston removal rate, WIWNU and estimated yield update live — so you can iterate toward an edge-balanced recipe.

Parameters
Wafer size
Area and average pressure scale with diameter
Downward force F
N
Pad material
IC1000 (XY-groove) is the industry default
Pad hardness (Shore D)
Platen speed ω
RPM
Retainer ring pressure
kPa
Suppresses edge over-pressure (typically 80-120% of mean P)
Slurry flow
mL/min
Process (film)
Switches the Preston coefficient Kp
Results
—
Avg pressure P (kPa)
—
Relative velocity V (m/s)
—
Removal rate MRR (Å/min)
—
Edge over-pressure (%)
—
WIWNU (%)
—
Estimated yield (%)
—
CMP platen / carrier / slurry — animation

The rotating platen carries the polishing pad while the wafer carrier presses the wafer down and slurry is dispensed from above. Colour indicates the within-wafer pressure distribution (centre: green → edge: red).

MRR vs pressure — Preston equation
Preston coefficient Kp by process
Theory & Key Formulas

$$MRR = K_p \cdot P \cdot V,\quad P = \frac{F}{A_{wafer}},\quad V = \omega \cdot r_{wafer}$$

Kp: Preston constant (Cu 2e-12, SiO2 1e-13 m²/N). P: average pressure [Pa]. V: relative velocity [m/s]. F: downward load [N]. A_wafer: wafer area [m²]. ω: rotation angular velocity [rad/s].

Semiconductor CMP Wafer Pressure Uniformity — Preston Removal Rate

🙋
"Chemical mechanical planarization"… isn't that just sandpapering the wafer? Why does the chemistry matter?
🎓
Mechanically, sure, it looks like sanding. But the "C" is critical: the slurry contains an oxidiser (H2O2 for Cu) that first oxidises the film, and then SiO2/Al2O3/Ce abrasive particles scrape off the softened layer. Two stages — chemistry first, then mechanics. That is why the Preston coefficient Kp is two or three orders larger than for pure mechanical polishing. On a 300mm Cu damascene step you can remove 6000Å — 0.6μm — in a single minute.
🙋
Got it. Looking at the MRR chart on the right, pushing the pressure higher just lifts the line. So can we just crank up the load in real fabs?
🎓
That is exactly the central CMP pain point. More load does raise MRR, but it also inflates "edge over-pressure" so the centre and the edge of the wafer remove at different rates. That shows up as WIWNU, and leading-edge logic demands 3-5% or yield collapses. So 300mm tools — Applied Materials Reflexion with the IPS or Mira head — split the wafer into 5-7 ring zones and drive each one with an independent back-pressure. That is the "multi-zone carrier" technology.
🙋
There's a "retainer ring pressure" slider on the left, and pushing it up drops WIWNU in the sim. Why does pressing a ring around the wafer make things uniform?
🎓
The pad is urethane — elastic — so just outside the wafer the pad sinks like a chamfer, and pressure concentrates at the wafer edge. The retainer ring (made from PEEK or PPS) sits at the same height immediately outside the wafer and squashes that sinking so the edge pressure peak disappears. Rings are consumables, replaced every ~200 hr. The rule of thumb is to set ring pressure to 80-120% of the average. Push past that and you create the opposite defect — edge roll-out, where only the outer ring of the wafer polishes too fast.
🙋
If I switch the process from SiO2 to Cu, the MRR jumps by 20× immediately. Is that purely the Kp value?
🎓
Yes — almost entirely Kp. SiO2 sits at 1e-13 while Cu is 2e-12, exactly 20×. The catch is that "fast removal = hard to control" — Cu CMP suffers from dishing (recessed line centres) and erosion (thinning of pattern-dense regions) at the same time. So endpoint detection is everything: Lam Research Lapis and Ebara F-REX combine motor-current change, NIR optical and friction-torque signals to stop the moment the oxide layer is exposed. At the 3nm GAA NS FET node, a single wafer goes through more than 30 CMP steps, and just one second of over-polish at any of them dents yield. That is the world we are in.

Frequently Asked Questions

The Preston equation is an empirical law derived by F.W. Preston in 1927 from glass polishing experiments. It states that the material removal rate (MRR) per unit time is proportional to the product of the contact pressure P and the relative sliding velocity V. The proportionality constant Kp (Preston coefficient) depends on the wafer film, slurry and pad combination, typically about 1×10⁻¹³ m²/N for SiO2 and 2×10⁻¹² m²/N for Cu — roughly one order of magnitude apart. This tool switches Kp by process and computes P and V from the load, wafer area and rotation speed.
WIWNU is generally defined as (max−min)/(2·mean) × 100% of the within-wafer film thickness. Leading-edge logic and memory require 3-5% or better. On 300mm wafers, the last 3mm of the edge dominates yield, so multi-zone carriers (Applied Materials IPS/Mira, Ebara F-REX ZP head) with 5+ independent back-pressure zones are standard to cancel edge over-pressure. This simulator flags WIWNU>10% as NG, 5-10% as a warning and below 5% as OK.
The retainer ring presses the area just outside the wafer to flatten the pad deformation and suppress edge over-pressure. In this tool, ringFactor = ring pressure / average pressure approaches 1 to drive edge over-pressure to zero. In practice, ring pressure is set to 80-120% of the average pressure. Going higher accelerates ring wear (PEEK/PPS ring life around 200 hr) and triggers edge roll-out — a different defect mode that thins the outermost band.
Metal CMP (Cu damascene, Co contact) has Preston coefficients one or two orders higher than SiO2, so removal is fast and over-polish quickly causes dishing (recessed line centres) and erosion (thinning of dense pattern regions). On top of that, Cu slurry chemistry (Cabot, Fujimi) is set by the H2O2 oxidiser / benzotriazole inhibitor balance — mechanical polishing alone cannot control it. Endpoint detection combines motor-current, NIR optical and friction-torque sensors so polishing stops the moment the oxide is exposed, minimising re-condition cycles.

Real-World Applications

Leading-edge logic (3nm GAA NS FET and beyond): A wafer at TSMC, Samsung, Intel or Rapidus goes through more than 30 CMP steps. STI (shallow-trench isolation), ILD (interlayer dielectric), Cu damascene wiring, Co contacts and now work-function-metal CMP for HKMG are all in play. The WIWNU<5% threshold this tool flags is the bare minimum — production lines aim for <3% with multi-zone back-pressure and real-time thickness monitoring.

3D NAND and DRAM: Kioxia, SK hynix and Micron stack more than 200 layers in 3D NAND and connect them with W plugs, making W CMP erosion control a direct yield lever. DRAM capacitor-area ILD CMP requires "stop on target" recipes built on SiO2 + chemical selectivity. The SiO2 / W presets here reflect those representative process windows.

Power devices (SiC, GaN): Surface flattening of 150-200mm SiC wafers is the new CMP frontier. SiC is harder than Si, so dedicated diamond-slurry low-speed / high-pressure recipes are used. Rohm, Mitsubishi Electric, Wolfspeed and ON Semi are mass-producing SiC modules. Kp values for SiC are not preset here, but the pressure / speed sensitivities are useful.

MEMS and advanced packaging: Demand for back-end CMP is exploding — TSV (through-silicon via) reveal CMP for Si interposers and pre-bonding wafer flattening (<1nm rms) for HBM hybrid bonding. SCREEN, Ebara and Tokyo Electron tools are used here with very low pressure and low RPM recipes.

Common Misconceptions and Pitfalls

The first trap is assuming the Preston equation explains everything. MRR = Kp·P·V is empirical: at low pressure the chemistry rate-limits and MRR collapses near zero (a "threshold pressure"), while at high pressure frictional heating deforms the pad and MRR rises non-linearly. Real recipes run in the linear band (typically 14-35 kPa) — the numbers here are for first-cut design. For Cu CMP, chemistry-rate-limited corrections (e.g. the Tseng-Wang model) are often used on top of plain Preston.

Second, treating the average pressure as the actual pressure everywhere. F/A is just a nominal value: real pressure distribution depends on ring pressure, head stiffness and pad hardness (the Shore D slider). On 300mm wafers an edge pressure 1.3-2× the centre is common, and that is the textbook cause of "centre OK, edge under- or over-polished" rejects. Running a 300mm process on an old 200mm tool without multi-zone control will always hit this wall.

Finally, "as long as slurry flow is high enough, it's fine" is wrong. Flow (mL/min) does drive chemistry, but what really matters is whether fresh abrasive keeps entering the wafer-pad interface. Platen rotation differential with the carrier, pad groove geometry (IC1000 XY-grv 800μm wide, 450μm deep) and diamond conditioning (3M, Saesol) work together; if conditioning is starved, doubling slurry flow will not lower WIWNU.

How to Use

  1. Enter downward force (500–2000 N) applied to the wafer carrier; typical 300 mm wafers require 1200 N for uniform oxide removal.
  2. Set pad hardness (Shore D 60–85); softer pads (60–70) improve conformability but reduce selectivity; harder pads (75–85) enhance tungsten polishing stability.
  3. Input rotation speed (30–150 RPM) for both wafer and platen; 100 RPM balances removal rate uniformity and thermal gradients on 450 mm wafers.
  4. Adjust carrier ring pressure (50–200 kPa) to suppress edge acceleration; higher pressures reduce edge over-pressure but risk dishing at die centers.
  5. Observe output metrics: average pressure distribution, relative velocity across pad, removal rate in Å/min, edge non-uniformity, and predicted yield impact.

Worked Example

300 mm SiO₂ CMP recipe: downward force 1100 N, pad hardness Shore D 72, platen speed 90 RPM, carrier ring pressure 120 kPa. Simulator outputs: average pressure 85 kPa, relative velocity 1.8 m/s, removal rate 3200 Å/min, edge over-pressure +8%, WIWNU 4.2%, estimated yield 94%. Lowering carrier ring to 90 kPa reduces edge over-pressure to +3% but increases WIWNU to 6.1%, dropping yield to 91%. This trade-off is critical for 450 mm nodes where edge bevels cost $50K+ per wafer.

Practical Notes

  1. Pad glazing occurs above 110 kPa average pressure on used pads (>50 hours); regenerate surface when removal rate drops below 2500 Å/min to restore uniformity.
  2. Thermal effects: 150 RPM on 450 mm wafers can induce 15–20°C center-to-edge temperature delta, causing non-linear pad deformation; reduce to 120 RPM if WIWNU exceeds 5%.
  3. Carrier ring design: eccentric rings (asymmetric 110/130 kPa) outperform fixed 120 kPa by 2–3% WIWNU on 300 mm with inter-die routing; not modeled here but verify experimentally.
  4. Slurry particle size (50–100 nm CeO₂) interacts nonlinearly with relative velocity; Preston equation breaks down above 2.5 m/s, causing unpredictable MRR spikes near wafer edges.