Calculate the switching loss and conduction loss of a power MOSFET used in DC-DC converters and motor drives in real time. Vary the voltage, current, frequency and rise/fall time to see the total dissipation and junction temperature rise, and get a quick read on the heatsink and switching-frequency choices.
Parameters
Drain voltage V_DS
V
Bus voltage blocked by the MOSFET when off
Drain current I_D
A
Load current flowing during the on state
Switching frequency f_sw
kHz
Rise + fall time t_sw
ns
Total transition time per switching event
On-resistance R_DS(on)
mΩ
Drain-source resistance in the fully-on state
Duty cycle D
Fraction of the period that the MOSFET is on
Results
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Energy per switch (µJ)
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Switching loss (W)
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Conduction loss (W)
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Total loss (W)
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Switching loss share (%)
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Junction temp rise (K)
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Switching waveform — V_DS / I_D overlap
Blue is drain voltage V_DS, orange is drain current I_D, and the red area is the instantaneous power p(t)=V_DS·I_D — its area per event equals the switching energy.
Energy per switching event E_sw and average switching loss P_sw. The triangular overlap area of V_DS and I_D equals E_sw, and the loss grows linearly with frequency f_sw.
$$P_{cond} = D\cdot I_{D}^{2}\cdot R_{DS(on)}$$
Conduction loss P_cond. I²R dissipation occurs only during the on time D·T. R_DS(on) rises with temperature, so use the value at the steady-state junction temperature.
Total loss P_tot and junction temperature rise ΔT_j. This tool assumes R_θJA = 30 K/W (TO-220 with a modest heatsink). Replace with your real datasheet thermal stack when checking a build.
What is MOSFET switching loss?
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A power MOSFET is essentially a resistor when on and an insulator when off, right? Both states sound low-loss, so why is "switching loss" such a big deal?
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Exactly. In the on state you only have I²·R_DS(on) of a few tens of milliohms times current squared; in the off state it is leakage current times voltage, essentially zero. The problem is the moment of transition. The MOSFET takes some tens to hundreds of nanoseconds to flip between off and on, and during that brief window V_DS and I_D are both large at the same time, so the instantaneous power p(t)=V_DS·I_D shoots up. It only lasts nanoseconds, but it happens at the switching frequency, so at high f_sw it becomes a serious source of heat.
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Then why not just lower the frequency? Why do designers insist on high frequencies?
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Good question. The motivation is "smaller magnetics and capacitors". The volume of a switching power supply is dominated by its inductors and capacitors. A 50 Hz linear transformer used to be the size of a lunchbox; the same job in a 100 kHz+ switcher fits in the palm of your hand. So the modern strategy is "push the frequency as high as switching loss will allow, to shrink the magnetics". This tool lets you see that trade-off directly.
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So if I sweep f_sw on the left from 10 kHz to 300 kHz, what happens?
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Try it. The conduction loss P_cond is independent of frequency, so it stays flat. The switching loss P_sw rises in a straight line with frequency. On the "Loss vs frequency" chart below you will see the two cross at some point. Above that crossover you are in the "switching-loss-dominated" regime. With these default values (100 V, 10 A, t_sw=50 ns) the crossover sits around 100 kHz, so above that the battle is all about cutting switching loss.
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And how do I cut switching loss? Lowering R_DS(on) does not help here?
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Right — R_DS(on) only affects conduction loss. To cut switching loss you have to shrink t_sw: (1) lower the gate resistance, (2) use a stronger gate driver, (3) pick a device with a smaller Q_g. The wide-bandgap devices everyone is talking about — SiC and GaN — win exactly here, because their t_sw is much shorter, so silicon MOSFETs capped at 100 kHz can be replaced with parts that run at 500 kHz or more. The catch is that shortening t_sw raises dV/dt and di/dt, which spikes EMI; you always pick the t_sw that just passes the EMI standard.
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It is nice that the junction temperature rise is shown too. Above what value should I worry?
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The absolute-max junction temperature of a silicon MOSFET is normally T_jmax = 150 °C, and for reliability the practical limit is 125 °C. Assuming a 25 °C ambient, that is a rise ΔT_j of about 100 K. With this tool's R_θJA = 30 K/W heatsink assumption, the allowable total loss is about (125-25)/30 ≈ 3.3 W. Cross that and you need a bigger heatsink, parallel devices, or a lower frequency.
Frequently Asked Questions
The energy lost per switching event is approximated by E_sw = (1/2)·V_DS·I_D·t_sw [J], where t_sw is the combined rise + fall time. It is the triangular overlap area where V_DS and I_D are both high. Multiplying by the switching frequency gives the average switching loss P_sw = E_sw·f_sw [W], which scales linearly with frequency. This tool uses exactly these two formulas.
It depends on frequency. At low frequencies (below a few kHz) conduction loss P_cond = D·I_D²·R_DS(on) dominates, so lowering on-resistance pays off. Above 100 kHz, switching loss P_sw = (1/2)·V_DS·I_D·t_sw·f_sw climbs quickly, and reducing the rise/fall time t_sw or picking a low-Q_g device becomes much more effective. The "switching loss share" card in this tool tells you which side of the design to focus on.
This tool assumes a thermal resistance R_θJA = 30 K/W, which is typical for a TO-220 package with a modest heatsink, and computes ΔT_j = P_total × R_θJA. A bare DPAK without a heatsink is more like 60-80 K/W; a large heatsink with forced air can drop to 5-15 K/W. For real builds, use the datasheet R_θJC (junction-to-case) plus R_θCS (interface) plus R_θSA (heatsink-to-ambient).
(1) Lower the gate resistance R_g to shorten t_sw, (2) increase the source/sink current of the gate driver, (3) move to wide-bandgap devices (SiC, GaN) with much smaller Q_g, and (4) reduce parasitic inductance so voltage overshoot does not force you to slow t_sw back down. Note that shortening t_sw too aggressively raises dV/dt and di/dt, so EMI rises sharply — the design is always a trade-off between loss and noise.
Real-World Applications
DC-DC converters (buck and boost): Smartphone chargers, laptop AC adapters and server power supplies — almost every switching power supply has MOSFET loss design at its core. Lifting the efficiency from 90% to 91% sounds small, but at data-center scale it is worth hundreds of thousands of dollars per year. Sweep f_sw, I_D and R_DS(on) in this tool to find the most efficient operating point before committing to silicon.
EV and industrial motor drives: Inverters in electric vehicles, industrial servo drives, and air-conditioner compressors handle hundreds of amps, so a small difference in on-resistance or switching time translates directly into heatsink size and package count. Many designs are migrating from silicon MOSFETs to SiC MOSFETs to shrink t_sw to roughly one-third, enabling smaller, more efficient drives. Compare SiC (t_sw=20 ns) with Si (t_sw=100 ns) in this tool to see the effect.
Solar and battery power-conditioning systems: Residential and industrial solar inverters and battery PCS units handle anywhere from kilowatts to hundreds of kilowatts, running 24/7, so a small efficiency gain becomes a large lifetime energy yield. Designers commonly balance conduction loss against switching loss to pick the optimum switching frequency, and this tool is ideal for that first cut.
High-frequency wireless power transfer and Qi charging: Qi wireless charging runs at hundreds of kHz, and industrial wireless power transfer reaches into the MHz range. At those frequencies switching loss dominates, and zero-voltage / zero-current soft-switching techniques become essential. Use this tool to size hard-switching loss and find the frequency threshold at which soft-switching pays off.
Common Misconceptions and Pitfalls
The biggest pitfall is "believing the datasheet E_on and E_off numbers will predict the real switching loss". The E_on / E_off values printed in datasheets are measured under specific test conditions: a fixed R_g, V_DS, I_D, temperature and inductive load. In a real circuit, (1) parasitic inductance causes voltage overshoot, (2) the body diode injects reverse-recovery charge, (3) the actual gate driver may not source/sink as much current as the datasheet test, and (4) Q_g and R_DS(on) both rise with temperature — any of these can easily double the loss. The (1/2)·V_DS·I_D·t_sw formula in this tool is the same idealisation, so apply a design margin of at least 1.5-2×.
Next, "R_DS(on) max from the datasheet is enough". R_DS(on) rises by roughly 1.8-2.2× between 25 °C and 150 °C for a silicon MOSFET, and conduction loss scales with it. That feeds back into temperature rise and creates a thermal runaway risk. Always use R_DS(on) at the expected operating junction temperature (typically 100-125 °C) and keep margin in the thermal design. This tool takes the 25 °C value as input, so apply your own temperature correction before judging.
Finally, "shorter t_sw is always better" is not true. Switching loss does scale linearly with t_sw, but shortening it sharpens dV/dt and di/dt, which (1) interact with parasitic inductance to create voltage overshoot and ringing, (2) drastically increase EMI (especially radiated noise above 30 MHz), (3) damage motor winding insulation through voltage reflection, and (4) push more common-mode current through stray capacitance to ground. In practice you set the maximum allowable dV/dt (a few kV/µs to a few tens of kV/µs to pass the standard) and back-calculate t_sw and gate resistance from there.
How to Use
Enter drain-source voltage (VDS) in volts—typical range 12–600V for industrial MOSFETs
Set drain current (ID) in amperes matching your DC-DC converter or motor drive load
Input switching frequency (FSW) in kHz—50–500kHz typical for buck converters, 20–100kHz for motor drives
Specify total switching time (TSW) in nanoseconds, accounting for rise time and fall time from datasheet
Click Calculate to obtain energy per switch, conduction loss, switching loss, and junction temperature rise
Worked Example
A 48V industrial DC-DC buck converter uses an IRF3205 MOSFET (RDS(on)=8mΩ at 25°C). At VDS=48V, ID=20A, FSW=100kHz, TSW=65ns: Energy per switch ≈ 31.2µJ, Switching loss ≈ 3.1W, Conduction loss ≈ 3.2W (20²×0.008), Total loss ≈ 6.3W, Switching loss share ≈ 49%, Junction temperature rise ≈ 38K above ambient assuming 0.166K/W thermal resistance.
Practical Notes
Higher TSW in older or larger MOSFETs dramatically increases switching loss—compare 65ns vs 120ns curves to justify upgrading to SiC MOSFETs
Conduction loss dominates at low FSW (<50kHz) and high RDS(on); switching loss dominates at FSW >200kHz
Use datasheet gate-charge QG instead of fixed TSW for precision; simulator assumes linear switching transition
Apply derating: MOSFET junction temperature must stay below 150°C; subtract 25°C ambient to find allowable loss budget