Pick the OSR, modulator order and quantizer bits of a ΣΔ ADC and see the in-band SNR, ENOB, sampling frequency and power update in real time. See for yourself how a single-bit quantizer with a high-order loop and large OSR can reach more than 20 effective bits.
Parameters
Application preset
Typical ΣΔ ADC application domains
Signal bandwidth (Nyquist BW)
kHz
Single-sided signal bandwidth BW
Modulator order L
Number of integrator stages (NTF=(1−z⁻¹)^L)
Oversampling ratio OSR
fs / (2·BW). Doubling gives 1.5(2L+1) bit gain
Quantizer bits N
1-bit is best for DAC linearity
Reference voltage V_ref
V
Results
—
Sampling freq fs (MHz)
—
Nyquist OSR
—
SNR (dB)
—
ENOB (bit)
—
Gain per OSR doubling (bit/oct)
—
Power (μW)
—
ΣΔ modulator block diagram — 1-bit bitstream
Input signal → summing node → L integrator stages → quantizer → output bitstream, with the feedback DAC closing the loop. The quantization noise is pushed to high frequencies by the NTF.
Resolution gain per OSR doubling. NTF is the noise transfer function (high-pass) realised by the L integrator stages.
ΣΔ ADC Oversampling — Noise Shaping SNR Design
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You see "ΣΔ ADC" on every datasheet, but how is it actually different from a normal ADC? And how can a 1-bit converter possibly record 24-bit audio?
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Good question. A SAR ADC does an honest job — each sample is resolved into N bits via successive comparisons, period. A ΣΔ ADC does the opposite: it spits out very coarse (often 1-bit) samples at a very high rate, and a digital filter behind it averages them. Each instant is rough, but average hundreds of them and you get an effective 24 bits. The trick is that the averaging is not flat — the loop pushes the quantization error to high frequencies first, then the decimation filter keeps only the clean low band. That is noise shaping.
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Noise shaping… I see the SNR rising fast when I raise OSR. I thought a normal ADC only gains 3 dB per OSR doubling?
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Right — a Nyquist ADC gains 3 dB (0.5 bit) per octave. A ΣΔ with L integrators has a noise transfer function (1−z⁻¹)^L, which strongly attenuates low frequencies and pushes noise upward. The net result is 1.5(2L+1) bit per octave: 1.5 bit/oct at L=1, 2.5 bit/oct at L=2, 3.5 bit/oct at L=3. Look at the default settings (L=2, OSR=256, 1-bit) — the SNR card shows around 115 dB and ENOB ≈ 18–19 bits. From a 1-bit input.
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It really does — ENOB is 18.9 bits. So if I push L=5 with the max OSR, I should get something even more amazing, right?
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That is where the trap is. The formula keeps climbing, but a single-loop 1-bit modulator at L≥3 is only conditionally stable, and at L≥4 it is essentially unstable. On silicon, the moment the input gets large (around ±0.6 V_ref or higher) the loop bursts into oscillation and the SNR collapses. Commercial parts stay at L=2–3 with 1-bit, or move to multi-bit (3–5 bit) quantizers, or use a MASH cascade of low-order loops to recover stability. When the verdict turns "warn", treat it as a sign that the configuration is unrealistic in a single loop.
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The presets (audio / precision / sensor / RF) have wildly different BW and OSR. How are they used in practice?
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ΣΔ thrives on narrow band, high resolution. Audio: BW = 20 kHz, OSR = 256, fs ≈ 10 MHz — parts like the AKM AK4499EX target 130 dB DR. Precision DC: BW = 1 kHz, OSR > 1000, ADCs such as TI ADS1262 deliver 32-bit output. Sensor nodes: BW around 100 Hz to keep power tiny. RF: bandpass ΣΔ digitises an IF directly inside SDRs and base stations. Same architecture, very different design points — slide the bandwidth and OSR around and watch the power card move as well.
Frequently Asked Questions
With noise shaping, doubling OSR gains 1.5(2L+1) effective bits. L=1 gives 9 dB/oct (1.5 bit/oct), L=2 gives 15 dB/oct (2.5 bit/oct) and L=3 gives 21 dB/oct (3.5 bit/oct). A plain Nyquist ADC only improves by 3 dB (0.5 bit/oct) per OSR doubling, which is why a low-resolution ΣΔ quantizer can still deliver very high ENOB.
A 1-bit quantizer (a single comparator) has only two output levels, so the internal feedback DAC is intrinsically linear — there are no element-mismatch errors to produce harmonic distortion. The quantization noise is large, but strong noise shaping (high L) and large OSR easily compensate. Almost every audio ΣΔ ADC uses a 1-bit modulator for that reason.
In theory higher L makes the noise-shaping slope steeper and the SNR better, but a single-loop 1-bit modulator becomes conditionally stable at L≥3 and essentially unstable at L≥4. Practical designs use (1) multi-bit quantizers (3–5 bits) at L=4–5, (2) MASH (Multi-stAge noise SHaping) cascades of lower-order loops, or (3) zero-optimised loop filters. Mainstream designs sit at L=2–3; high-end audio reaches L=4–6 via MASH and multi-bit.
ΣΔ wins for narrow band, high resolution (audio 24-bit/192 kHz, precision DC 32-bit/1 kHz, sensors 16-bit/100 Hz). SAR wins for medium band, medium resolution, low latency (12–18 bits, several MSPS, control loops). The decimation filter of a ΣΔ ADC adds a large group delay, which is fatal for tight control loops but invisible to audio and instrumentation. For RF or pulse capture, pipeline or flash ADCs are preferred.
Real-world Applications
Audio ADCs / DACs: Practically all digital audio — CD (44.1 kHz/16-bit), DAT, Hi-Res (96/192 kHz) and DSD (5.6 MHz/1-bit) — is built on ΣΔ. Parts like AKM AK4499EX, ESS ES9039PRO and Cirrus Logic CS43198 push 130–140 dB DR and THD+N near −120 dB. Typical recipes are 4th–6th-order multi-bit modulators at OSR 64–256, followed by 8–16× decimation to 24-bit / 192 kHz.
Precision DC instrumentation: TI ADS1262/ADS1263 (32-bit / 38 kSPS), Analog Devices AD7768 (24-bit / 256 kSPS) and Maxim MAX11270 drive strain gauges, thermocouples, RTDs and pH electrodes. Bandwidths of 1 Hz – a few kHz and OSR 1024–8192 deliver 22–24 effective bits. The MUX-channel settling time of the digital filter is the key system constraint.
Sensors and wearables: Accelerometers, ECG analog front ends, bone-conduction mics and capacitive MEMS microphones (PDM output) all embed 1st–3rd-order ΣΔ modulators in ASICs. Smartphone MEMS mics emit a 1-bit PDM stream directly into the SoC, where a CIC + FIR decimator turns it into 16–24-bit PCM at 48 kHz.
RF and software-defined radio: Cellular base stations and SDR receivers use bandpass ΣΔ ADCs to digitise an IF (tens to hundreds of MHz) directly, with a digital down-converter behind. Placing the NTF zeros on the RF channel of interest gives very high SNR exactly there. LTE / 5G small cells, radar receivers and EW front-ends increasingly adopt this approach.
Common Misconceptions and Pitfalls
The biggest trap is treating the theoretical SNR formula as the silicon SNR. The SNR = 6.02N + 1.76 + 10(2L+1)log₁₀OSR − 10log₁₀(π^{2L}/(2L+1)) used here assumes white quantization noise, a perfectly stable modulator and zero clock jitter. Real chips lose to thermal noise (opamp + kT/C of the sampling cap), clock jitter SNR_jitter = −20log₁₀(2πf_in·σ_jitter), reference noise and (in multi-bit) DAC element mismatch. If the simulated SNR matches measurement within ~10 dB, the design is fine; a 20 dB gap means one of these noise sources dominates.
Second, "higher L is always better" is wrong. A single-loop 1-bit modulator at L ≥ 3 is conditionally stable: when the input exceeds about ±0.6·V_ref the loop oscillates and SNR drops to noise floor. Commercial parts realistically tolerate ±0.7 V_ref input; driving them at full-scale 0 dBFS produces a sudden distortion increase. Mitigations are (1) back the input off by ~3 dB, (2) move to a multi-bit quantizer, or (3) cascade low-order loops in a MASH 1-1-1 / 2-1-1 topology. The "warn" verdict in this tool lights up whenever L ≥ 4 is combined with a 1-bit quantizer.
Third, "raising OSR only buys resolution" is misleading. Doubling OSR also doubles fs, roughly doubles analog power (clocked analog scales with fs), increases decimation-filter gate count and power, and adds tens to hundreds of samples of group delay. That delay is harmless in audio or instrumentation but eats phase margin in control loops. Choosing a ΣΔ ADC means accepting "huge resolution traded for group delay" — keep that trade-off in mind whenever you reach for one.
How to Use
Set the signal bandwidth (bwNum) in kHz—typical audio is 20 kHz, medical ultrasound is 5–8 MHz.
Enter oversampling ratio (OSR_ratio) between 4 and 256; higher OSR pushes quantization noise out of band.
Select modulator order (1st, 2nd, or 3rd); 2nd-order provides 9 dB SNR gain per octave, 3rd-order gives 15 dB/octave.