Every analog-to-digital converter has to round a continuous voltage to one of 2^N discrete codes. This tool computes the quantization step Q, RMS quantization noise, full-scale SNR (the famous 6.02N+1.76 dB), signal SNR, oversampling gain and ENOB in real time as you change the bit count, full-scale voltage, signal amplitude, sampling rate and signal bandwidth.
Parameters
Bit count N
bit
Resolution. Each extra bit improves SNR by about 6 dB
Full-scale voltage V_FS
V
ADC input span. V_FS/2^N is one LSB
Signal amplitude V_sig
V
Peak amplitude of the input sine. Keep below full scale
Sampling frequency f_s
Hz
Samples per second
Signal bandwidth BW
Hz
Highest frequency of interest. f_s/(2 BW) is the oversampling ratio
Results
—
Quantization step Q (µV)
—
RMS quantization noise (µV)
—
Full-scale SNR (dB)
—
Signal SNR (dB)
—
Oversampling gain (dB)
—
ENOB (bits)
—
Continuous signal vs quantized waveform — one-period sweep
Blue: continuous input sine. Orange: the N-bit ADC staircase. The thin red line below is the difference (quantization error — the seed of the noise).
Signal SNR for an input of amplitude V_sig, and the oversampling processing gain. Anything above f_s/(2 BW) = 1 can be filtered out by a digital low-pass.
Effective number of bits — the measured SNR expressed as an equivalent ideal bit count. Dither linearises a quantizer's small-signal behaviour.
What is ADC quantization noise?
🙋
An A/D converter just turns a voltage into a number, right? So what is "quantization noise"? It does not sound like a regular electrical noise.
🎓
Good instinct — this is not thermal noise that sneaks in physically. It is much more fundamental. An ADC can only output one of 2^N codes, so any analog input has to be rounded to the nearest code. A 16-bit ADC has 65 536 codes; on a 5 V range one step is 5/65 536 ≈ 76 µV. Every voltage between two steps becomes the same code. That rounding error wiggles around as the signal changes and looks just like a small random noise added to the output. That is quantization noise.
🙋
Got it — an unavoidable noise. But when I push "Bit count N" on the left, SNR shoots up. It goes up by 6 dB per bit. Is that a famous formula?
🎓
Very famous: SNR = 6.02·N + 1.76 dB. It is the theoretical ceiling for an ideal ADC. The derivation is short — assume the quantization error is uniform over ±Q/2, so its RMS is Q/√12; the RMS of a full-scale sine (peak V_FS/2) is (V_FS/2)/√2; take the ratio in dB and you land on 6.02N+1.76. Every added bit means 6 dB more dynamic range, i.e. 4x lower noise power. A 16-bit ADC tops out at 98 dB; 24-bit at 146 dB, although real 24-bit parts run into thermal noise around 21 ENOB.
🙋
On the bottom-right chart, total SNR keeps climbing as the oversampling ratio increases. The bit count is fixed — where does the extra SNR come from?
🎓
That is the magic of oversampling. The total quantization noise power Q²/12 is fixed, but it is spread uniformly over 0 to f_s/2. Push f_s way above the signal bandwidth BW, and only the fraction BW/(f_s/2) of the noise lives in the signal band — the rest is filtered out digitally. The processing gain is 10·log10(f_s/2BW) dB. 4x oversampling → +6 dB, equivalent to one bit. A delta-sigma ADC takes this to 256× or 1024×, adds noise shaping, and turns a 1-bit quantizer into a 24-bit-class converter.
🙋
What does ENOB mean? Is it different from N?
🎓
ENOB = Effective Number Of Bits. Even if a datasheet says "16 bit", the real SNR rarely reaches 98 dB. If you measure SNR = 90 dB, then ENOB = (90 − 1.76)/6.02 ≈ 14.7 bits — the bottom 1.3 bits are buried in noise. The right way to compare ADCs is by SNR / SINAD / ENOB at the sample rate and input frequency you care about, not by the marketing bit number.
🙋
The theory note mentions "dither". Adding noise on purpose to improve accuracy sounds contradictory.
🎓
Counter-intuitive but real. A quantizer is a hard nonlinear element for small signals: it stays glued to the same code. Add a tiny random noise (about Q peak) just before quantization and the average behaviour becomes a smooth straight line. Each sample is noisier, but the DC bias and harmonic distortion of the bare quantizer disappear into broadband noise that averages out beautifully. Audio DACs, instrumentation, delta-sigma converters and image-processing error-diffusion all rely on dither.
Frequently Asked Questions
An N-bit ADC divides its full-scale range V_FS into 2^N equal codes, so one step is Q = V_FS/2^N. The quantization error is assumed uniformly distributed over (-Q/2, +Q/2), so its RMS value is Q/sqrt(12). The RMS value of a full-scale sine wave (peak V_FS/2) is (V_FS/2)/sqrt(2). Taking the ratio in dB gives SNR = 20 log10((V_FS/2)/sqrt(2) / (V_FS/2^N/sqrt(12))) = 20 log10(2^N * sqrt(3/2)) = 6.02 N + 1.76 dB. That is why every extra bit buys about 6 dB of dynamic range.
The total quantization noise power Q^2/12 does not depend on the sampling rate, but it is spread uniformly over the band 0 to f_s/2. If you sample much faster than the signal needs, only the fraction BW/(f_s/2) of that noise sits in the signal band; the rest is removed by a digital low-pass filter. The resulting improvement is 10 log10(f_s/(2 BW)) dB — the processing gain. A 4x oversampling buys +6 dB (one extra bit), and a delta-sigma ADC uses hundreds of times oversampling plus noise shaping to reach 24-bit-class SNR from a 1-bit quantizer.
ENOB is the measured SNR re-expressed as an equivalent ideal-bit count: ENOB = (SNR_measured - 1.76)/6.02 bits. A 16-bit ADC has an ideal SNR of 98 dB, but if thermal noise, distortion, clock jitter and supply noise drag the measured SNR down to 90 dB, ENOB is only about 14.7 bits — the bottom 1.3 bits are buried in noise. The datasheet 'resolution' is just the code spacing; ENOB is the resolution you can actually use. When selecting a high-precision ADC, compare ENOB (or SNR / SINAD), never the marketing bit number.
Counter-intuitively, yes. Adding a small random noise of order Q just before quantization linearises the average behaviour of the quantizer on small signals. Each individual sample is noisier, but the systematic DC bias and harmonic distortion produced by an undithered quantizer disappear into broadband noise, which is much easier to filter or average out. Dither is a standard trick in audio DACs, instrumentation, delta-sigma converters and image processing (error-diffusion dither) whenever the quality of low-level signals matters.
Real-World Applications
Consumer and pro audio (CD, hi-res, streaming): The CD standard is 16-bit / 44.1 kHz, giving an ideal SNR of 98 dB — well above the dynamic range of human hearing, so quantization noise is essentially inaudible. Hi-res 24-bit / 96 kHz brings the theoretical SNR to 146 dB, leaving big editing margins, although thermal noise pins real-world DACs around 20-21 ENOB. When mastering for 16-bit delivery, dither is added on small signals so that fade-outs and quiet passages do not develop audible quantization distortion.
Test & measurement (oscilloscopes, data loggers, LCR meters): Low-frequency precision instruments use 16-24 bit delta-sigma ADCs, while wide-bandwidth scopes use 8-12 bit pipeline or flash ADCs. A 1 GS/s oscilloscope is typically only 8 bits (256 vertical codes), and pulls in oversampling and waveform averaging to raise the effective resolution. By contrast, a microvolt-level strain-gauge logger uses a 24-bit delta-sigma part with a 100 Hz signal bandwidth, yielding 20+ ENOB.
Communications (wireless receivers, SDR, 5G base stations): A receiver ADC has to digitise a weak desired signal in the presence of strong interferers, so dynamic range (≈ SNR + margin) is the figure of merit. Base stations use 14-16 bit ADCs sampling at hundreds of MHz, then claim processing gain through digital down-conversion. In a software-defined radio (SDR) the product of bit count and sample rate (the FoM) basically sets receiver performance.
Control and sensor interfaces: Servo current sensing typically uses 12-16 bit ADCs; temperature, pressure and strain-gauge front-ends prefer 16-24 bit delta-sigma converters. The design flow is to match the ADC range to the sensor full-scale, then back-calculate the minimum ENOB needed for the application (e.g. 0.1 °C resolution needs roughly 10 ENOB). Running a quick check with a tool like this prevents over-specifying the ADC and inflating the bill of materials.
Common Misconceptions and Pitfalls
The biggest pitfall is picking an ADC by its bit count alone. A "24-bit" part with an ENOB of 18 is effectively an 18-bit converter. Even worse, some fast 16-bit ADCs only deliver 12 ENOB. Always read the SNR / SINAD / ENOB at the input frequency and sample rate of interest. This tool shows the ideal ADC ceiling; real chips can only fall short of it, never beat it.
Next, assuming you can keep boosting SNR forever by raising f_s. The textbook says you gain 10·log10(f_s/2BW) dB, but in real silicon the aperture jitter of the sample-and-hold becomes the dominant noise above some frequency, and SNR levels off — or even drops. The jitter-limited SNR is 20·log10(1/(2π f_in t_j)); even a very good ADC with t_j = 1 ps maxes out around 64 dB at 100 MHz input. You cannot have "fast, high resolution and low noise" all at once.
Finally, "drive the input all the way to full scale and SNR is maximised" is only half true. Push the signal past V_FS and the ADC clips, and harmonic distortion explodes. In practice you set the maximum input a few dB below full scale (typically -3 to -6 dBFS) so even transient peaks do not clip. You lose a few dB of SNR but avoid the much worse distortion. In this tool you can watch the signal SNR rise as V_sig approaches V_FS, then fall sharply on small signals — a faithful picture of the real ADC trade-off where finding the right input level is part of the craft.
How to Use
Set the ADC resolution in bits (e.g., 12, 16, 24) using the bitsNum input; this defines the total number of discrete quantization levels as 2^N.
Enter the full-scale input range in volts (e.g., 10V, 5V) via bitsRange to establish the quantization step Q = FSR/2^N.
Specify your signal amplitude in volts and sampling frequency in Hz using ampNum and fsampNum respectively.
Optionally configure oversampling by setting fsNum (oversampling factor) to calculate noise shaping gains; leave at 1 for no oversampling.
The simulator automatically calculates quantization step, RMS noise (Q/√12), full-scale SNR, signal SNR, oversampling gain, and effective number of bits (ENOB).
Worked Example
A 16-bit ADC with 10V full-scale range digitizes a 1V amplitude sine wave at 48 kHz sampling rate with 4× oversampling. Quantization step Q = 10V/65536 = 152.6 µV. RMS quantization noise = 152.6/√12 = 44.1 µV. Full-scale SNR = 6.02×16 + 1.76 = 98.8 dB. Signal SNR ≈ 86.4 dB (6 dB loss from amplitude ratio). Oversampling gain = 10×log₁₀(4) = 6.02 dB reduces effective noise floor by 6 dB per octave. ENOB = 16 bits at 1V signal level. At 1 mV signal, ENOB drops to ~13 bits due to insufficient quantization levels.