Design a Chemical Mechanical Planarization (CMP) process for semiconductor wafers using Preston's equation RR = K_p·P·v. Adjust pad pressure, relative velocity and the material x slurry combination to see the removal rate, total removal, WIWNU, throughput and per-wafer cost update in real time.
Parameters
Pad pressure P
kPa
Down-force per area on the wafer. Typical 20-50 kPa
Relative velocity v
m/s
Pad-to-wafer sliding speed. WIWNU degrades above 1.5 m/s
Polished material
Main films polished in semiconductor processing
Slurry
Abrasive particle chemistry
Preston constant K_p
m²/N
Lumped constant for material x slurry x pad
Process time t
min
Wafer radius R
mm
150 mm = 300 mm wafer; 100 mm = 200 mm wafer
Results
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Base RR (nm/min)
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Material-corrected RR (nm/min)
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Total removal (nm)
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WIWNU non-uniformity (%)
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Throughput (wafers/hr)
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Cost per wafer (USD)
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CMP tool cross-section animation
The carrier head presses the wafer down onto a rotating pad while slurry (coloured drops) is dispensed. Surface roughness flattens to nm scale over the process cycle.
Preston equation (1927). K_p: Preston constant [m²/N] (~1e-13 for SiO₂/silica), P: pad pressure [Pa], v: relative velocity [m/s]. The native SI unit of RR is m/s; the tool converts to nm/min (×60×10⁹).
Material x slurry compatibility multiplier k (e.g. SiO₂ x ceria = 3.0, Cu x alumina = 1.0, Low-k x silica = 0.1). Δh is total removal [nm] over process time t [min].
Semiconductor CMP — Preston Equation and Removal Rate
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CMP stands for "Chemical Mechanical Planarization", but is it really just grinding a wafer with abrasive? How do you ever get nm-level flatness from that?
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Half right, half wrong. CMP runs a wafer face-down on a polyurethane pad while a slurry — tens-of-nm abrasive particles in a reactive liquid — flows underneath. The trick is the "chemical" part. For SiO₂ the slurry creates a thin Si-OH softened layer, and silica abrasive shaves only that softened layer off. Pure mechanical grinding would damage the substrate, but with the chemical softening you remove just a few nm at a time — perfect for planarising a wafer to single-nm uniformity.
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OK, and the removal rate is RR = K_p·P·v from the Preston equation, right? Isn't that suspiciously simple? Slurry flow, pad type, temperature... there must be more variables.
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Good catch. Preston's 1927 equation for glass polishing predicts the removal rate from pressure and velocity alone. In reality slurry flow, abrasive concentration, pad stiffness, temperature and wafer bow all matter. But what engineers actually do is sweep all of those effects into the single constant K_p and use the equation to predict trends with P and v. That's why a 100-year-old empirical relation is still the standard model. When a new material or slurry appears, "first measure K_p" is the very first step.
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When I switch the polished material from SiO₂ to Cu or W, the removal rate changes a lot even with the same K_p. What's that correction?
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That's the material x slurry compatibility factor k. SiO₂ with ceria (CeO₂) abrasive sees a unique chemical reaction — Ce⁴⁺ directly attacks Si-O-Si bonds and removes oxide about 3x faster than silica abrasive. That's why ceria slurries dominate Shallow Trench Isolation CMP. Cu only polishes when it is first oxidised, so its standard slurry is hydrogen-peroxide plus alumina. Tungsten needs an even stronger oxidiser plus alumina, while Low-k films are so mechanically fragile that you have to polish slowly at low pressure regardless of slurry. The matrix in this tool is a deliberately coarse approximation of that industry experience.
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WIWNU means "within-wafer non-uniformity", correct? Why does my number get worse when I push relative velocity above 1.5 m/s?
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The pad can't keep up. At high speed the slurry doesn't have time to redistribute on the pad surface, and the outer ring of a 300 mm wafer (whose linear speed is even higher) is polished too aggressively. Leading nodes require WIWNU below 3% across the whole wafer, and you only get there by combining (1) a pad conditioner that constantly refreshes the pad, (2) a multi-zone carrier head that varies pressure radially, and (3) End-Point Detection — optical or motor-torque based — to stop exactly on the stopper layer. Applied Materials' Reflexion, Ebara's F-REX and Lam's SP100 are the workhorse 300 mm CMP tools.
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It's interesting that the simulator also reports throughput and cost per wafer. How do engineers use that?
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In the early stage of process development you want to know whether you can meet a target removal in the allowed cycle time without blowing the cost budget. CMP is one of the most consumables-heavy steps in a fab: slurry plus pad alone is roughly USD 5-10 per wafer pass, and amortising the tool brings the all-in cost to USD 30-50. The classic trade-off is "raise P and v to shorten time" versus "preserve WIWNU and pad life". A quick model like this one shows the trade-off before any wafer has been polished.
Frequently Asked Questions
It is an empirical relation proposed by F. Preston in 1927 for glass polishing: the removal rate RR is proportional to the pad pressure P and the relative velocity v between pad and wafer. The proportionality constant K_p (the Preston constant) lumps together material, slurry and pad effects; for SiO2 with colloidal silica it is about 1e-13 m^2/N. In semiconductor CMP the equation is evaluated in SI units (m/s, Pa) and then converted to nm/min, which is exactly what this tool does.
No. Each film has its own preferred abrasive. SiO2 has a specific chemical reaction with ceria (CeO2) that gives more than 3x the removal rate of silica, which is why ceria slurries dominate STI CMP. Cu damascene wiring requires an oxidizer-loaded alumina slurry that chemically oxidizes Cu and mechanically removes it. W plugs use alumina plus a strong oxidant; poly-Si uses silica; Low-k films are mechanically fragile and need very low pressure and slow chemistry. This tool embeds a coarse material x slurry correction matrix.
Leading-edge EUV nodes (3 nm / 2 nm) require WIWNU below 3%, and production lines aim for 2%. Legacy 28 nm and above typically passes at around 5%. WIWNU degrades when (1) the relative velocity is too high for the pad to follow, (2) pad conditioning is inadequate, (3) slurry distribution is non-uniform, or (4) the head pressure profile is poorly tuned. In this tool the WIWNU estimate increases above 1.5 m/s of relative velocity.
Experimentally. A blanket film is polished at a fixed P and v for a known time; the film thickness change is measured (e.g. by WDXRF or ellipsometry); the removal rate RR follows; and K_p = RR / (P v). Slurry vendors quote typical values but every fab tunes K_p for its own tool, pad and consumable batch. This simulator allows K_p between 1e-15 and 1e-12 m^2/N with 1e-13 as the SiO2/silica reference.
Real-world Applications
STI (Shallow Trench Isolation) oxide planarisation: the SiO₂ fill that electrically isolates adjacent transistors is CMP-planarised until the surface is mirror-flat. This step is mandatory in every logic and memory product at 28 nm and below, and high-selectivity ceria-based slurries (oxide-to-nitride ratio > 30:1) are the de-facto standard.
Cu damascene interconnect planarisation: trenches are etched into a SiO₂ (or Low-k) dielectric, filled with electroplated Cu, and the overburden Cu plus the Ta barrier is CMP-removed. Every logic chip at 0.13 μm and below uses this scheme. Balancing dishing of wide lines against erosion of dense arrays is the engineer's everyday challenge.
3D NAND / DRAM stack-building: modern 3D NAND with 200+ memory layers, and capacitor formation in DRAM, each require CMP at almost every layer. A single wafer can see more than 30 CMP steps, so shortening cycle time has a direct impact on cost-per-bit.
Power semiconductors SiC and GaN: SiC is roughly 10x harder than Si and its removal rate with colloidal silica is only about 1 nm/min, so dedicated approaches such as electrochemical CMP (ECMP) and high-temperature CMP have been developed. This tool is calibrated for Si-based processes, but pushing K_p toward 1e-15 lets you feel SiC-like behaviour qualitatively.
Common Misconceptions and Pitfalls
The most common mistake is to treat the Preston equation as a precise predictor of removal rate. It is an empirical model and several nonlinear effects sit on top: (1) at very low pressure the process becomes "chemically rate-limited" and the P-dependence weakens; (2) at very high velocity a hydrodynamic slurry film forms between pad and wafer (hydroplaning) and the rate drops; (3) K_p drifts with pad life and conditioning. This tool is for understanding qualitative trends; in real production K_p must always be measured experimentally on the actual tool/pad/slurry stack.
The second pitfall is the reasoning "higher pressure means faster CMP, so I save cycle time". RR is linear in P, but high pressure brings serious side effects: Cu/Al scratching across patterned layers, Low-k film delamination, accelerated pad wear, and elevated wafer stress that can crack die at the bevel. Modern logic processes at 28 nm and below run at 20 kPa or less, and Low-k inter-metal layers at 10 kPa or less — "low pressure as a religion" is the rule. Setting P = 100 kPa in this tool may look fine numerically, but in a real fab it would almost certainly produce yield-killing defects.
The third pitfall is believing that controlling the average removal rate is enough to control final film thickness. Thickness uniformity (WIWNU) is determined not by the mean RR but by its spatial distribution across the wafer. Even with perfect end-point detection, locations that hit the endpoint first get over-polished while late locations leave residue. The truly hard part of CMP is managing the in-plane distribution through pad-groove design, retainer-ring pressure and slurry-nozzle placement. Treat this tool's WIWNU estimate as a coarse guide; the real WIWNU in a fab depends on many additional factors.
How to Use
Enter pad pressure in kPa (typical range: 20–100 kPa for oxide, 40–80 kPa for copper).
Set relative velocity in m/s between pad and wafer (standard: 0.5–1.5 m/s for polishing head rotation).
Input Preston K constant for your slurry chemistry (oxide: 1.2–2.8 × 10⁻⁶ µm³/J; Cu: 0.8–1.6 × 10⁻⁶ µm³/J).
Define process time in minutes (typically 30–120 min for full-field planarization).
Review base removal rate, material-corrected rate, total removal depth, WIWNU uniformity, throughput, and cost metrics.
Worked Example
Oxide CMP on 300 mm wafer: pad pressure 60 kPa, relative velocity 1.2 m/s, Preston K = 2.0 × 10⁻⁶ µm³/J, process time 45 min. Base RR = (60 × 1.2 × 2.0 × 10⁻⁶) = 144 nm/min. Total removal = 144 × 45 = 6480 nm (6.48 µm). If WIWNU target is 5%, actual 4.2% indicates good pad conditioning. Throughput: 8 wafers/hr at 45 min cycle. Cost per wafer: slurry ($2.50) + pad wear (
How to Use
Enter pad pressure in kPa (typical range: 20–100 kPa for oxide, 40–80 kPa for copper).
Set relative velocity in m/s between pad and wafer (standard: 0.5–1.5 m/s for polishing head rotation).
Input Preston K constant for your slurry chemistry (oxide: 1.2–2.8 × 10⁻⁶ µm³/J; Cu: 0.8–1.6 × 10⁻⁶ µm³/J).
Define process time in minutes (typically 30–120 min for full-field planarization).
Review base removal rate, material-corrected rate, total removal depth, WIWNU uniformity, throughput, and cost metrics.
Worked Example
Oxide CMP on 300 mm wafer: pad pressure 60 kPa, relative velocity 1.2 m/s, Preston K = 2.0 × 10⁻⁶ µm³/J, process time 45 min. Base RR = (60 × 1.2 × 2.0 × 10⁻⁶) = 144 nm/min. Total removal = 144 × 45 = 6480 nm (6.48 µm). If WIWNU target is 5%, actual 4.2% indicates good pad conditioning. Throughput: 8 wafers/hr at 45 min cycle. Cost per wafer: slurry ($2.50) + pad wear ($1.80) + labor ($0.70) = $5.00 per wafer.
Practical Notes
Increase pad pressure incrementally; exceeding 80 kPa degrades pad life and causes edge erosion on 28 nm nodes and below.
Velocity above 1.8 m/s generates excessive heat; monitor slurry temperature to prevent thermal drift in damascene fill processes.
WIWNU above 8% signals pad glazing; refresh conditioning or reduce dwell time at pattern edges to improve within-wafer uniformity.
Cu polishing requires lower K constants due to electro-chemical barriers; use barrier layer removal sequences to optimize step coverage.
Track removal rate drift over 200 wafer runs; K constant degrades ~15% as pad hardens, requiring slurry replenishment or pad replacement.
.80) + labor ($0.70) = $5.00 per wafer.
Practical Notes
Increase pad pressure incrementally; exceeding 80 kPa degrades pad life and causes edge erosion on 28 nm nodes and below.
Velocity above 1.8 m/s generates excessive heat; monitor slurry temperature to prevent thermal drift in damascene fill processes.
WIWNU above 8% signals pad glazing; refresh conditioning or reduce dwell time at pattern edges to improve within-wafer uniformity.
Cu polishing requires lower K constants due to electro-chemical barriers; use barrier layer removal sequences to optimize step coverage.
Track removal rate drift over 200 wafer runs; K constant degrades ~15% as pad hardens, requiring slurry replenishment or pad replacement.