Coplanar Waveguide (CPW) Simulator Back
RF / Microwave Simulator

Coplanar Waveguide (CPW) Simulator — Characteristic Impedance Z_0

Visualize the characteristic impedance of a coplanar waveguide using the Wheeler/Hilberg elliptic-integral approximation. Change the center-strip width W, gap G and dielectric constant to develop intuition for 50-ohm RF routing.

Parameters
Center-strip width W
mm
Gap G
mm
Dielectric constant ε_r
Frequency f
GHz

Wheeler/Hilberg approximation assuming an infinite-thick substrate, a thin perfect conductor and wide ground planes on both sides.

Results
Aspect ratio k = W/(W+2G)
Effective permittivity ε_eff
Characteristic impedance Z_0
Guided wavelength λ_g (at f)
CPW Cross Section

Top: center strip W (yellow) / gap G / adjacent grounds (gray). Bottom: dielectric substrate ε_r. Arcs: schematic E-field lines.

Z_0 vs Aspect Ratio k = W/(W+2G)

Blue curve: Z_0(k) at the current ε_r / red dashed line: 50-ohm target / yellow dot: current operating point.

Theory & Key Formulas

A coplanar waveguide (CPW) is a transmission line that places a center conductor W and two ground planes on the same surface, separated by gaps G. The characteristic impedance depends on the aspect ratio k and the complete elliptic-integral ratio K(k)/K(k').

Aspect ratio k and its complement k':

$$k = \frac{W}{W + 2G}, \qquad k' = \sqrt{1 - k^2}$$

Hilberg's closed-form approximation of K(k)/K(k') (accuracy ≈ 8 ppm):

$$\frac{K(k)}{K(k')} = \begin{cases} \dfrac{\pi}{\ln\!\left(2\,\dfrac{1+\sqrt{k'}}{1-\sqrt{k'}}\right)} & (0 \le k \le \tfrac{1}{\sqrt{2}}) \\[2pt] \dfrac{1}{\pi}\ln\!\left(2\,\dfrac{1+\sqrt{k}}{1-\sqrt{k}}\right) & (\tfrac{1}{\sqrt{2}} \le k \le 1) \end{cases}$$

Effective permittivity and characteristic impedance on an infinite-thick substrate:

$$\varepsilon_\text{eff} \approx \frac{\varepsilon_r + 1}{2}, \qquad Z_0 = \frac{30\pi}{\sqrt{\varepsilon_\text{eff}}}\,\frac{K(k')}{K(k)}$$

Guided wavelength (from phase velocity c/√ε_eff):

$$\lambda_g = \frac{c}{f\sqrt{\varepsilon_\text{eff}}}$$

What is the Coplanar Waveguide (CPW) Simulator

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CPW is new to me. How is it different from a microstrip line?
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Roughly speaking, a microstrip is a sandwich — signal line on top of the substrate, ground plane on the bottom. A coplanar waveguide (CPW) puts the signal line and the grounds on the same surface. The center strip W has a gap G on each side, and beyond that gap there is ground. In the cross section above you can see the yellow center strip with the gray grounds right next to it. Because you don't have to go through a via to reach ground, CPW is a favorite at millimeter-wave frequencies.
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OK. So how do you pick W and G to get Z_0 = 50 ohms?
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Here's the interesting bit: the CPW characteristic impedance doesn't care about W and G separately, only about the ratio k = W/(W+2G). For a microstrip, W/h (width over substrate thickness) matters, but a CPW lives entirely on the surface, so it is scale-invariant. Try scaling W and G together by the same factor in the simulator — Z_0 doesn't budge.
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You're right! W = 1 mm with G = 0.6 mm gives the same Z_0 as the defaults. Scale really doesn't matter.
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Right. In practice you pick W and G inside the constraints of your process (say, W ≥ 0.1 mm and G ≥ 0.075 mm) so that the target k comes out. The defaults (W = 0.5, G = 0.3, εr = 4.3) give k ≈ 0.45 and Z_0 ≈ 78 Ω. To hit 50 Ω you need a larger k, that is, a stronger W:G bias (3:1 or even 4:1). Try W = 0.6, G = 0.1 and you'll see Z_0 come down close to 50 Ω.
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And what is the guided wavelength λ_g? It gets shorter as I raise the frequency.
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Good catch. In a CPW the fields straddle the substrate-air interface, so they see an averaged ε_eff ≈ (ε_r+1)/2. The phase velocity is c/√ε_eff, slower than in vacuum, so the wavelength at a given frequency is shorter than the free-space wavelength. At 5 GHz on FR-4 (εr = 4.3) the free-space wavelength is 60 mm but on the CPW it shrinks to about 37 mm. When you design matching networks and distributed filters this λ_g is your ruler.

Frequently Asked Questions

At millimeter-wave frequencies (30 to 300 GHz) the parasitic inductance of a via can no longer be ignored, and a microstrip needs vias to bring the ground return up to the surface. In a CPW the return current flows in the ground conductors that sit right next to the signal line, so it never goes through a via. Parasitic L is small and discontinuities are less reflective. In semiconductor processes (GaAs and SiGe MMICs) where backside metallization is hard, CPW is the default since everything happens on the top surface.
CBCPW (Conductor-Backed CPW) has an additional ground plane on the back of the substrate. It gives mechanical stiffness and shielding, but the top and bottom grounds can form a parallel-plate resonance ("parallel-plate mode"). Suppressing that mode requires a fence of vias stitching the two grounds together. This tool assumes a pure CPW on an infinite-thick substrate (no back ground); the Z_0 of a CBCPW on a finite substrate is typically 5 to 10 percent lower than the value predicted here.
This tool assumes a thin perfect conductor. Real copper foils (18 μm, 35 μm, etc.) have finite thickness, and the skin effect at high frequencies forces the current onto the conductor surface. If the conductor thickness is on the order of 10 percent of G, the effect on Z_0 is only one or two ohms, but for thick copper (70 μm and up) or narrow gaps (G < 100 μm) you need to correct for it. Conductor loss scales as α_c ∝ √f and dominates with dielectric loss above 5 GHz. Critical designs should be confirmed by measurement or a 3D EM solver.
The formulas in this tool assume the side ground planes extend to infinity. In practice, if the ground width is at least about 5×(W+2G) the infinite-ground approximation is accurate to within one percent. Below that you have a finite-ground CPW (FGCPW), and Z_0 rises slightly (less capacitance to the distant ground). If layout constraints force you into a narrow-ground geometry, use dedicated FGCPW formulas (see Simons' textbook) or an EM solver.

Real-World Applications

5G and 6G millimeter-wave modules: In phased-array antennas and RFIC interconnects at 28, 39 and 60 GHz, CPW is the standard transmission-line geometry. Via-less ground access lets designers route many elements densely while keeping parasitic inductance small. The internal layout of a smartphone or base-station mmWave module is full of CPW-style traces with grounds running alongside the signal lines.

MMICs (Monolithic Microwave Integrated Circuits): RF and microwave ICs on GaAs, SiGe or GaN almost always rely on CPW because the back of the wafer cannot easily be patterned. The input/output traces of amplifiers, mixers and switches, the matching-network lines and the bias routes are all CPW. Designers use closed-form approximations like the one in this tool to pick initial dimensions and then refine with Sonnet or ADS Momentum.

Automotive radar and autonomous sensing: Automotive radars in the 76 to 81 GHz band rely on CPW to connect antenna arrays to the front-end electronics. With a wavelength of only a few millimeters, a fraction of a millimeter in trace length translates into significant phase shift. Use this tool to estimate λ_g, then back out the physical lengths from the required phase differences when shaping the radiation pattern.

RF probing and test fixtures: Ground-Signal-Ground (GSG) probes are essentially CPW landing structures pressed onto the wafer. The launch lines into the device under test are naturally CPW as well, and matching them to 50 ohms is what makes the measurement clean and free of reflections. A quick CPW impedance estimate from this tool is useful when sketching the first revision of a test fixture.

Common Misconceptions and Cautions

The most common misconception is to think that "making W wider always lowers Z_0". Yes, if you only change W, then k = W/(W+2G) goes up and Z_0 goes down — but the CPW characteristic impedance depends only on the ratio. Scale W and G by the same factor and Z_0 stays the same. In real designs you usually start from the minimum gap G allowed by your process and then size W to hit the target k. Try doubling W and G together in the simulator and watch Z_0 stay put. That scale-invariance is the essence of CPW design.

The next pitfall is to assume that ε_eff = (ε_r+1)/2 always holds. That simple formula is exact only under the ideal assumptions of an infinite-thick substrate, infinite ground planes and a thin conductor. In real boards the substrate has a finite thickness h (typically 0.1 to 1.6 mm), so if h is small compared with G, the back of the board "leaks" air and the actual ε_eff is smaller. On the other hand, CBCPW (with a back ground plane) approaches ε_eff → ε_r at low frequencies because of the parallel-plate mode. Treat the value from this tool as a first-cut estimate and lock in final dimensions with formulas that include substrate thickness (Simons, Wadell) or with an EM solver.

Finally, beware of the assumption that "matching k is enough to make the line behave as predicted". The closed-form impedance ignores (1) surface roughness losses, (2) photolithography and etch tolerances of ±5 to 10 μm, (3) loading by the soldermask, and (4) discontinuities at bond wires or connectors. Low-grade laminates like FR-4 also exhibit ε_r variations of ±0.3, which can easily move Z_0 by ±5 ohms. Once you've picked nominal dimensions in this tool, fabricate a test coupon, measure with a TDR or VNA, and iterate. That loop is what turns a paper design into a working 50-ohm CPW.