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Semiconductor Etch
Plasma Etch Selectivity & Anisotropy Simulator
An interactive tool for SiO₂, Si, poly-Si and Al thin-film patterning by reactive ion etching (RIE). Change the gas chemistry, plasma and bias power, pressure and flow, and instantly see etch rate, selectivity, anisotropy, depth, mask loss and aspect ratio — the building blocks of a semiconductor dry-etch recipe.
Parameters
Etch gas
Main reactive chemistry & typical target
Target film
Film to be etched
Source power
W
Bias power
W
More bias = stronger ion directionality (anisotropy↑, selectivity↓)
Chamber pressure
mTorr
Lower pressure stretches the ion mean-free path and boosts anisotropy
Gas flow
sccm
Etch time
s
Results
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Etch rate (nm/min)
—
Selectivity (vs PR)
—
Anisotropy (%)
—
Etch depth (nm)
—
Mask loss (nm)
—
Aspect ratio (—)
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Etch cross-section animation
Purple haze is the plasma, yellow is the photoresist mask, blue is the target film and cyan arrows are incident ions. The vertical-vs-lateral ratio of the ions sets the anisotropy.
Gas × Film selectivity matrix (vs PR)
Anisotropy vs chamber pressure
Theory & Key Formulas
$$\text{Selectivity} = \frac{ER_{\text{target}}}{ER_{\text{mask}}},\qquad A = 1 - \frac{ER_{\text{lat}}}{ER_{\text{vert}}}$$
ER: etch rate (nm/min); A: anisotropy (1 = perfectly vertical, 0 = isotropic). Low pressure and high bias both raise A.
Empirical scaling: square-root dependence on source power P_src (W) and linear correction with bias power P_bias (W).
$$d = ER_{\text{actual}}\cdot t/60,\qquad AR = d/W_{\text{feature}}$$
Etch depth d (nm; t in seconds) and aspect ratio AR (feature width W = 200 nm assumed). Bosch DRIE targets AR > 30.
Plasma etch selectivity and undercut — anisotropic-etch design
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"Plasma etching" is that mysterious step inside semiconductor fabs, right? You pump in fluorine or chlorine gas and somehow it carves metal and silicon. How does a gas etch a film?
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Good question. Ordinary wet etching (think HF in water) is pure chemistry — the solution dissolves the film. RIE (Reactive Ion Etching) is one level smarter. RF power inside the chamber ionises the gas, producing both fluorine radicals (F*) and cations (CF₃⁺). The radicals react on the surface, e.g. SiO₂ + 4F → SiF₄↑, turning the film into a volatile gas. At the same time the cations are accelerated downward and physically bombard the surface, removing reaction products that would otherwise block the chemistry. Chemistry plus physical bombardment — that is the essence of dry etching.
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So radicals and ions do different jobs. When I switch the gas from CF₄+O₂ to Cl₂+BCl₃ on the left, the SiO₂ selectivity collapses. Why?
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That is the heart of selectivity engineering. Cl reacts readily with Si and Al, but the O-Si bond in SiO₂ is too strong for Cl to break efficiently. So Cl₂ plasma etches SiO₂ at only about 30 nm/min while it cuts Al at 600 nm/min. That is exactly what you exploit when you want to pattern Al lines without damaging the SiO₂ underneath. If you want to etch the SiO₂ itself, you switch back to a CF₄+O₂ recipe that gives you plenty of F radicals. The recipe rule of thumb is simple: pick a gas that reacts with the film you want gone and not with the layer underneath.
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The anisotropy curve plunges when I raise pressure. I want vertical sidewalls — why does pressure matter?
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At low pressure the ion mean-free path is long, so ions accelerated across the sheath (the boundary between the plasma and the wafer) hit the surface almost straight down. Physical sputtering only works on horizontal surfaces, the radicals alone barely touch the vertical sidewalls, and you end up with nearly vertical walls. Raise the pressure and collisions scatter the ions; their incidence angle spreads, sidewalls take impact too, and you get lateral etch — undercut. At the 5 nm logic node A must be above 0.95, so etchers run at 5-20 mTorr with hundreds of watts of bias.
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When I pick DRIE Bosch the behaviour suddenly looks different. How is it not just another RIE?
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Bosch is the specialist DRIE flow for MEMS and TSVs. It alternates SF₆ (etch) and C₄F₈ (passivation) every 2-5 seconds. During the SF₆ step Si etches isotropically a tiny bit; the next C₄F₈ step deposits a Teflon-like CFx polymer on the sidewalls. The next SF₆ step breaks the polymer at the bottom thanks to ion bombardment, so Si etches again, but the sidewall polymer survives and prevents lateral attack. Repeat 100-1000 cycles and you get vertical through-holes with AR 30-100. The micrometre-scale "scallops" on the sidewall are the Bosch fingerprint. Without Bosch you simply cannot build comb-drive inertial sensors or inkjet nozzles.
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People keep talking about ALE (Atomic Layer Etching). Is that still a kind of RIE?
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ALE is an evolution of RIE in which chemical adsorption and physical removal are separated in time. First a single monolayer of, say, Cl₂ adsorbs (self-limiting). Then low-energy Ar⁺ ions gently knock off only that adsorbed layer. Each cycle advances 0.1-0.3 nm, but cycle count sets the depth precisely, giving ±0.1 nm uniformity across a 300 mm wafer. EUV-node GAA transistors, recess etches in advanced DRAM and channel formation in 3D NAND all rely on ALE. Lam Research Kiyo, Applied Materials Sym3 and TEL Tactras Vigus all ship with ALE modes built in.
Frequently asked questions
Selectivity is the dimensionless ratio of the etch rate of the target film over the etch rate of the mask (or underlying film). For SiO₂ etched in a CF₄+O₂ plasma with a photoresist mask, if SiO₂ etches at 200 nm/min and the resist at 100 nm/min, the selectivity is 2.0. When selectivity falls below 1 the mask is consumed faster than the target film, so the pattern collapses before the etch is complete. Deep trench and thick-film etches typically require selectivity of 5-20, while Bosch DRIE may need values above 100.
Anisotropy A = 1 − (lateral etch rate / vertical etch rate). A=1 means a perfectly vertical sidewall (the ideal dry etch), A=0 is fully isotropic (wet-etch like). Sub-micron ICs require A > 0.9 so neighbouring lines stay separated. Lateral etching (undercut) shrinks the line width and shifts the final device parameters (on-resistance, threshold voltage). Low pressure (< 20 mTorr) and high bias (more directional ion bombardment) improve anisotropy, but trade off against selectivity.
Bosch is the classic Deep Reactive Ion Etching (DRIE) approach: it alternates short SF₆ etch steps (a few seconds of Si etching) with C₄F₈ steps that deposit a Teflon-like passivation film on the sidewalls. Each cycle advances the etch vertically while the sidewall film blocks lateral attack, allowing aspect ratios of 30-100+. MEMS through-silicon vias (TSV) and inertial-sensor comb structures cannot be made without Bosch. The characteristic micrometre-scale sidewall "scallops" are the Bosch fingerprint and are smoothed with O₂ plasma or dilute HF when needed.
ALE removes one atomic layer at a time by alternating a self-limiting chemical activation step (for example Cl₂ adsorption) with a low-energy Ar⁺ ion-removal step. Each cycle advances only 0.1-0.3 nm, but the depth is set by the number of cycles, giving exceptional uniformity, selectivity and anisotropy. It is used at EUV nodes (5 nm and below) for logic, recess etches in advanced DRAM/3D-NAND and the channel-release step in GAA transistors. Compared with classical RIE that etches sub-micron in seconds, ALE controls a few nm over minutes — truly an "atomic-layer chisel".
Real-world applications
Logic and memory front-end-of-line: at 5 nm and 3 nm logic nodes (TSMC N5/N3, Samsung 3GAE, Intel 18A) almost every gate definition, contact-hole opening and metal patterning is done with RIE + ALE. SiO₂ contact holes use CF₄/CHF₃ chemistry, Si fins use HBr/Cl₂, low-k dielectrics for Cu damascene use C₄F₈, and a single wafer sees 30-50 separate etch process steps.
3D NAND and DRAM: 176- and 232-layer 3D-NAND requires through-stack channel holes (100 nm diameter, 10 µm deep, AR > 100) etched in a single pass. F-based gases, deep-UV pulsing and hard masks combine in the most difficult HARC (High Aspect Ratio Contact) etch in the industry. Lam Research's Sense.i platform dominates this step and uses Bosch-like multistep recipes to hold sidewall taper within ±0.5°.
MEMS and advanced packaging TSVs: comb drives in inertial sensors (IMUs), inkjet nozzles and through-silicon vias for HBM memory all rely on Bosch DRIE to cut holes 5-50 µm wide and 100-500 µm deep. Scallop period (200-500 nm) and sidewall angle (89.5° ± 0.5°) are the key quality metrics. Dedicated ICP-RIE tools from SPTS (KLA), Plasma-Therm and TEL serve this market.
Compound and power semiconductors: mesa formation and gate-recess steps for GaN HEMTs and SiC inverters use Cl₂/BCl₃, etching SiC at 100-500 nm/min and GaN at 50-200 nm/min. SiC is so chemically inert that selectivity above 5 demands strong physical sputtering, so 200-500 W bias is standard. Lam Versys Metal and AMAT Producer Etch are the workhorses here.
Common misconceptions and watch-outs
The first trap is the assumption that "etch rate scales linearly with power". Doubling source power does increase radical density, but the sheath voltage drops, so ion bombardment weakens and etch rate ends up scaling roughly as the square root of power. If you raise bias to compensate, the photoresist mask is consumed about as fast as the target, so selectivity collapses. This simulator uses a √P_src scaling and linear bias correction precisely to discourage the "just turn the power up" mindset, which fails on deep trenches when the mask vanishes before pattern transfer is complete.
The second trap is believing "higher anisotropy is always better". Yes, ICs need A > 0.9, but pushing low pressure and high bias too far causes (1) a large selectivity hit, (2) plasma damage from excessive ion energy (interface defects, Vth shift) and (3) charging-induced sidewall tilt (an inverted-V groove). Production processes settle for A ≈ 0.92-0.95 and recover yield with multi-step recipes (main → over-etch → soft landing). The A value here is an idealisation — always cross-check against SEM cross-sections of real wafers.
The third trap is treating "etch depth = rate × time" as an exact prediction. In reality (1) dense regions starve their neighbours of radicals so etch slower than isolated openings (loading), (2) the bottoms of deep features see fewer ions because of ARDE (Aspect Ratio Dependent Etching), and (3) wafer heating distorts the resist. Bosch DRIE typically leaves a 5-10% depth difference between wafer centre and edge, which production lines correct with thickness monitors and ±5% etch-time tweaks. Treat this tool as a first-order recipe-sizing aid only.
How to Use
Set source power (13.56 MHz RF) between 100–500 W to control ion generation and radical flux at the wafer surface.
Adjust bias power (0–200 W) to modulate ion energy and directionality; higher bias increases anisotropy and etch rate.
Configure chamber pressure (10–100 mTorr) and gas flow (20–100 sccm CF₄/O₂ or Cl₂ mixtures) to tune selectivity and uniformity.
Observe real-time etch rate (nm/min), selectivity ratios (SiO₂:resist, Si:mask), anisotropy percentage, and mask erosion to optimize selectivity and aspect ratio.
Worked Example
For SiO₂ patterning with CF₄ RIE: source power 300 W, bias power 100 W, chamber pressure 50 mTorr, gas flow 50 sccm yields etch rate ~180 nm/min on oxide with ~5:1 selectivity versus photoresist, 87% anisotropy factor. After 6 minute etch, SiO₂ depth reaches 1080 nm with photoresist mask loss of 180 nm and final aspect ratio of 2.1. Doubling bias power to 200 W increases anisotropy to 94% and etch rate to 210 nm/min but reduces selectivity to 4.2:1 due to increased ion bombardment.
Practical Notes
Higher source power (400+ W) with CF₄ generates more fluorine radicals but increases polymer deposition on sidewalls; balance with bias power for vertical profiles.
Selectivity over photoresist degrades below 30 mTorr pressure due to ion-dominated chemistry; maintain 40–60 mTorr for stable SiO₂:PR selectivity >4:1.
Polysilicon undercut occurs with O₂-rich mixtures above 200 W source power; use Cl₂ chemistry at 150–250 W for <10% isotropic component in gate etching.
Monitor aspect ratio and mask loss during deep via etching (>2 µm); reduce bias power by 20–30 W per 1 µm depth to prevent sidewall damage and resist taper.