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Semiconductor Manufacturing

Semiconductor Yield & Defect Density Simulator

Compute wafer yield with four classic models — Poisson, Murphy, Seeds (Negative Binomial) and Bose-Einstein. Adjust die size, defect density D0, critical layer count and design rule to see A·D, yield Y, dies-per-wafer and cost-per-good-die update in real time.

Parameters
Die size A
mm²
Single-chip area. Larger dies lose yield exponentially.
Defect density D0
/cm²
Killer defects per cm². Mature processes run 0.05-0.1.
Critical layers
layers
Photo/etch critical steps. EUV 3nm needs 70-90.
Yield model
Poisson assumes uniform defects; others correct for clusters.
Design rule (CD)
nm
Minimum line width. EUV: 3-7nm. DUV: 28-65nm.
Wafer diameter
mm
Leading nodes use 300mm. Next-gen 450mm is being discussed.
Cluster coefficient α
For the Seeds model. Smaller α = more clustered defects.
Results
—
D0·A (dimensionless)
—
Yield Y (%)
—
Dies per wafer
—
Good dies
—
Cost per good die (USD)
—
Killer defect size (nm)
—
Wafer map — die matrix and defects

Schematic 300mm wafer with die matrix. Green = good die, red = failing die, white dots = detected defects. The right meter shows yield Y.

Yield Y vs die size — 4-model comparison
Current condition — 4-model predictions
Theory & Key Formulas

$$Y_{Poisson} = e^{-AD},\quad Y_{Murphy} = \left(\frac{1-e^{-AD}}{AD}\right)^{2},\quad Y_{Seeds} = \left(1+\frac{AD}{\alpha}\right)^{-\alpha}$$

A: die area (cm²), D: defect density (/cm²), α: cluster coefficient. Bose-Einstein gives $Y = 1/(1+AD)$.

$$N_{die} = \left\lfloor\frac{\pi (D_w/2)^2 \cdot u}{A}\right\rfloor,\quad N_{good} = \lfloor N_{die}\cdot Y\rfloor,\quad C_{good} = \frac{C_{wafer}}{N_{good}}$$

Wafer diameter $D_w$, utilisation $u\approx0.85$, wafer cost $C_{wafer}$ (~$13k for EUV sub-10nm, ~$8k for DUV).

Semiconductor Yield — Defect Density with Murphy/Poisson Models

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I keep hearing "TSMC hit 80% yield at 3nm". What does that 80% actually mean?
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In short, it's the fraction of dies on a wafer that pass test and can ship. If a 300mm wafer holds 600 dies and 480 of them pass, yield Y = 480/600 = 80%. The wafer cost is divided by good dies to get cost-per-good-die — so the same chip at 50% yield costs 1.6× more than at 80%. That's why every fab obsesses over the last few percent of yield.
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And what actually makes a die "bad"? Broken wires or something?
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Yes — open or shorted metal, drifted transistor characteristics, gate-oxide leakage. They all come from "defects": particles in the resist, etch residues, even photon shot noise in lithography. If one killer-size defect lands inside a die, that die is lost. The Poisson formula Y = exp(-A·D) assumes defects are uniformly random in space, so doubling the die area halves the yield (roughly). It's the textbook starting point.
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When I switch from Poisson to Murphy or Seeds in the left panel, the yield jumps around for the same A·D. Which one is right?
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Good catch. In real fabs, defects aren't uniform — they cluster near the wafer edge, around a chuck mark, or on one specific scanner shot. Poisson is too pessimistic for big dies in that regime. Murphy adds a gamma-distributed assumption, and Seeds (Negative Binomial) lets you dial in a cluster coefficient α directly. Most modern fabs find α ≈ 1.5-2 fits inline-inspection data best. Bose-Einstein is the very conservative lower bound.
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There's also a "critical layers" slider. Pushing it from 30 to 70 tanks the yield. So more layers is worse?
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Right. EUV 3nm stacks roughly 70-90 critical layers. Even at 99% yield per layer, 0.99^70 ≈ 49% line yield. That's why fabs spend insane money on cleanroom Cu particles, pellicles and inline metrology — pushing the single-layer yield from 99% to 99.9% buys a huge multiplier. Mature 28nm only has about 20 critical layers, which is why mature nodes still produce 90%+ even with looser defect control.
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So how do you actually improve yield in practice?
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Three levers. (1) Lower D: tool maintenance, mask cleanliness, pellicle replacement, chamber conditioning. (2) Lower A: split the chip into chiplets — AMD Ryzen CCDs, Apple M Ultra, Nvidia B200 all use this trick to make giant logic shippable. (3) Break clusters: KLA and Applied wafer-inspection tools feed defect maps into AI to find "killer hotspots" and optimise tool-maintenance cycles. A monolithic H100 lives on (1)+(3); the AMD chiplet philosophy lives on (2).

Frequently Asked Questions

The most basic estimator is the Poisson model Y = exp(-A·D), where A is the die area (cm²) and D is the defect density (defects/cm²). Yield drops exponentially with larger dies or higher defect counts. Real processes show defect clustering, so the Murphy model [(1-exp(-AD))/(AD)]² and the Seeds Negative Binomial model (1+AD/α)^(-α) correct for clusters. This simulator lets you switch between Poisson, Murphy, Seeds and Bose-Einstein and compare A·D, yield Y, dies-per-wafer and cost-per-good-die in real time.
As the design rule (CD) shrinks, the killer defect size also shrinks to roughly CD/3. At 3nm, 1nm-scale particles and line-edge roughness (LER) become killer defects, and stochastic effects such as resist photon shot noise dominate. On top of that, the critical layer count exceeds 70, so even 99% per-layer yield gives only 0.99^70 ≈ 49% line yield. This is why TSMC N3 took more than two years to reach 80% production yield.
Murphy assumes a gamma-distributed defect density and gives more realistic yield than Poisson for large SoC, GPU and FPGA dies where A·D is high. The Negative Binomial (Seeds) model adds an independent cluster coefficient α — smaller α means more clustered defects. In production, α is fitted from inline inspection defect maps (e.g. KLA tools) and covers a wider operating range than Murphy. Try sweeping α between 0.5 and 5 here to see how yield shifts even at constant A·D.
Wafer area (π·(D/2)²) is multiplied by an 85% utilisation factor (to account for edge die loss) and divided by die area, then floored to get total dies per wafer. Good dies = floor(dies × Y). Cost-per-good-die = wafer cost / good dies, using $13,000 per wafer for EUV/sub-10nm (CD\lt 10) and $8,000 otherwise. Real cost depends on mask sets, tool depreciation and the yield-improvement curve, so treat this as a relative-comparison tool.

Real-world Applications

Foundry production planning: TSMC, Samsung and Intel Foundry use Murphy/Seeds models when ramping a new node to forecast the yield ramp curve, sizing tool capex, mask sets and contract pricing. Going from N5 to N3, the plan to take D0 from 0.5 to 0.1 /cm² within six months drove the order books for ASML EUV scanners, Lam etchers and KLA inspection tools.

Chiplet economics: An AMD Ryzen Core Complex Die (CCD) is ~70mm², while an Apple M2 Ultra is a monolithic ~800mm². At the same D=0.1/cm², the Poisson yields are roughly 93% and 45% respectively. The "Yield vs die size" chart here visualises why splitting into chiplets dramatically improves cost-per-good-die. The same logic drives Nvidia H100/B200 towards CoWoS integration.

Defectivity engineering and tool maintenance: KLA and Applied Materials wafer-inspection systems produce defect maps. Fitting the Seeds α to those maps reveals whether clusters disappeared after a chamber clean. Sweeping α from 0.8 (heavily clustered) to 3 (uniform) in this tool shows how strongly tool condition couples to yield — which is why AI-driven anomaly detection is a hot capex item.

New materials and transistors: Decisions on GAA FET, Backside Power Delivery and High-NA EUV depend on how fast initial yield (often 30%) can ramp to 75%. Pinning CD at 3nm and gradually lowering D from 0.5 to 0.05 in this tool reproduces the classic yield-ramp story. Intel 18A and Samsung 2GAP compete exactly in this regime.

Common Misconceptions & Caveats

The biggest mistake is using Poisson alone. Poisson assumes ideally uniform random defects, but real fabs have edge clustering, scanner-shot-dependent defects and chuck-induced patterns. Poisson is too pessimistic for large dies and indistinguishable from Murphy/Seeds for small dies — so people mistakenly conclude "all the models agree". For any die above ~200mm² (modern GPUs, SoCs), recompute with Murphy or Seeds and use the gap to Poisson as a margin.

Another trap is treating multilayer processes as a single-layer model. This tool keeps Y_die for simplicity, but real logic has independent D0 per layer and the line yield is ΠY_layer. At EUV 3nm with 80 layers, even 99.5% per layer gives only 0.995^80 ≈ 67%. Skipping maintenance on one single tool can collapse the line yield overnight — that's why critical-layer count must be folded into cost models, not just A·D.

Finally, low cost-per-good-die ≠ low TCO. This calculator considers only wafer cost, but real cost loads mask sets ($30M+ at 3nm), design IP, tool depreciation (~$200M per EUV scanner), test, packaging and yield-engineering headcount. The same $25 per good die in a 30% early-yield line vs an 80% mature line implies vastly different margins. Decide on TCO across the full ramp curve, not on wafer cost alone.

How to Use

  1. Enter die size in mm² (e.g., 15 for a 3.87×3.87 mm die) and defect density in defects/cm² (typical range 0.01–0.5 for mature 28nm nodes).
  2. Specify the number of critical layers exposed to defects and minimum critical dimension in nm (e.g., 22nm for advanced logic, 180nm for analog).
  3. Select a yield model: Poisson (simple exponential), Murphy (clustering), Seeds/Negative Binomial (spatial correlation), or Bose-Einstein (quantum-inspired vacancy clustering).
  4. Review outputs: D₀·A product, yield percentage, good dies per 300mm wafer, and cost per good die assuming $5000 wafer cost.

Worked Example

A 7nm FinFET die measuring 45 mm² with defect density 0.08 defects/cm² across 8 critical metallization layers and 7nm minimum feature size. Poisson model yields Y = exp(−0.08 × 45 × 8) = exp(−28.8) ≈ 2.4% yield, approximately 25 good dies per 300mm wafer (700 total), costing $200/good die. Switching to Murphy's model with clustering factor α=1.2 reduces yield to 1.8% due to spatial correlation. Killer defect threshold = √(7 nm) × critical dimension ≈ 18.5 nm.

Practical Notes

  1. Poisson underestimates defects in real fabs where particles cluster; use Murphy or Seeds for 7nm/5nm nodes with >0.03 defects/cm².
  2. Cost-per-good-die spikes nonlinearly: moving from 0.05 to 0.10 defects/cm² on a 50 mm² die triples unit cost under exponential yield falloff.
  3. Critical dimension matters: 22nm analog dies tolerate 10× higher defect density than 3nm logic due to larger killer defect size windows.
  4. Use Bose-Einstein model only when defects show quantum clustering patterns (rare edge-case vacuum-chamber contamination).