Design a phase-locked loop (PLL) that synthesises a high, accurately-spaced frequency by multiplying a clean reference by the divider ratio N. Adjust the reference, divider ratio, loop bandwidth and damping ratio to see the output frequency, lock time, overshoot and phase margin update in real time, and find a synthesiser that locks fast and stays stable.
Parameters
Reference frequency f_ref
kHz
Stable reference, e.g. from a crystal oscillator
Divider ratio N
÷N divider in the feedback path; the multiplier
Loop bandwidth
kHz
Closed-loop −3 dB bandwidth; wider = faster lock
Damping ratio ζ
Speed vs overshoot trade-off; 0.707 is standard
VCO sensitivity K_VCO
MHz/V
VCO frequency change per volt of control voltage
Phase-detector gain K_PD
V/rad
Phase-detector output voltage per radian of error
Results
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Output frequency f_out (MHz)
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Loop natural frequency ωn (rad/s)
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Lock (settling) time (µs)
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Overshoot (%)
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Phase margin (deg)
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Stability verdict
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PLL block diagram — locking animation
Signal travels reference → phase detector → loop filter → VCO → output, while the ÷N divider in the feedback path returns the output to the phase detector. The lower panel shows the VCO frequency converging to N·f_ref.
The output frequency f_out is the reference f_ref multiplied by the divider ratio N. The lock (settling) time t_lock is inversely proportional to the product of the damping ratio ζ and the natural frequency ωn.
Overshoot of the locking transient, fixed by the damping ratio ζ alone; for ζ≥1 (over-damped) there is no overshoot. ωn is the loop natural frequency and ζ the damping ratio of the second-order loop, related to the loop bandwidth by ω_3dB = ωn·√(1+2ζ²+√((1+2ζ²)²+1)).
What is the Phase-Locked Loop (PLL) Simulator?
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"PLL" shows up everywhere in radio and CPU descriptions. What does the circuit actually do?
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In plain terms, it is "a machine that takes a copy of a clean reference frequency and scales it up by whatever ratio you want". Inside there are four parts: a phase detector, a loop filter and a VCO (voltage-controlled oscillator) wired into a ring, with a ÷N divider sitting in the feedback path back to the phase detector. The phase detector compares the reference against the divided-down output, and if they differ it adjusts the VCO's voltage. Once the divided output matches the reference exactly, the VCO itself is oscillating at N times the reference.
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So that's why the output is N times the reference. When I move the divider ratio N on the left, the output frequency f_out scales straight up with it.
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Exactly — f_out = N·f_ref. That is why a PLL is called a "frequency synthesiser". Set the reference to 1 MHz and step N through 100, 101, 102… and you get 100 MHz, 101 MHz, 102 MHz in 1 MHz steps. Radio and smartphone tuning is exactly this: switching N to pick a channel. The power of it is that the precision of a single crystal can be copied and handed out at hundreds of times its frequency.
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When you switch N, does the output jump to the target frequency instantly?
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No, and that is the interesting part — locking takes time. The instant you change N, the output starts heading toward the new target, but it overshoots and swings back before settling. The time to settle is the "lock (settling) time". Look at the transient chart below. A small damping ratio ζ approaches the target fast but overshoots a lot and rings; a large ζ is smooth but slow. The standard is ζ ≈ 0.707, the sweet spot with about 4% overshoot and 65° phase margin — a good balance of speed and stability.
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If I want it faster I just widen the loop bandwidth, right? Then why not make it wide for everything?
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That is the trade-off. Widening the loop bandwidth does lock faster, and it makes the loop suppress the VCO's own phase noise more strongly. But in exchange, spurs on the reference and divider jitter pass straight through the loop and leak into the output. Narrow the bandwidth and the output gets cleaner but the lock is slow. In practice you set the bandwidth by the tug-of-war between "how fast do I need to switch channels" and "how clean must the output be" — usually below one tenth of the reference frequency.
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There's also a phase-margin number. What does that one measure?
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Think of phase margin as the loop's "stability reserve". A feedback loop oscillates if the phase rotates to −180° while the gain is still above one. Phase margin is the angle that says how far you are from −180° at the frequency where the gain crosses unity. For a 2nd-order PLL it is fixed by the damping ratio ζ — about 65° at ζ=0.707 and 76° at ζ=1. Below 45° the transient gets shaky and risky; around 60° gives a comfortable, stable design. Move ζ and you will see phase margin and overshoot change together.
Frequently Asked Questions
A PLL places a divider (÷N) in the feedback path so the output frequency is locked to an integer multiple of the reference, f_out = N·f_ref. The phase detector compares the reference with the divided-down output and drives the VCO (voltage-controlled oscillator) until the two match. Once locked, the divided output equals the reference frequency, so the VCO itself oscillates at N·f_ref. With a 1 MHz reference and N=100 the output is 100 MHz. Changing N by one synthesises frequencies spaced by f_ref — the heart of radio tuning and CPU clock generation.
The damping ratio ζ sets the trade-off between locking speed and overshoot/ringing. A small ζ locks fast but overshoots heavily and rings, while a large ζ is smooth but locks slowly. The standard compromise is ζ ≈ 0.707 (Butterworth response), giving about 4% overshoot and roughly 65° phase margin. Below ζ ≈ 0.4 the loop rings badly and looks under-damped; above ζ ≈ 1.2 it is over-damped and too slow. Most real designs sit in the ζ = 0.7 to 1.0 range.
A wider loop bandwidth locks (settles) faster and lets the loop suppress the VCO's own phase noise more strongly. The cost is that reference spurs, reference noise and divider jitter pass straight through the loop and appear at the output. A narrower bandwidth locks more slowly but rejects reference spurs and noise better. In practice the bandwidth is set by the tug-of-war between the lock-time requirement and the output phase-noise/spur requirement — a common rule of thumb is to keep it below one tenth of the reference frequency.
Phase margin is a stability metric: it is how far the phase of the open-loop transfer function is from −180° at the frequency where the gain crosses unity (0 dB). A small phase margin makes the loop prone to oscillation and gives a ringing transient. For a 2nd-order PLL the phase margin is fixed by the damping ratio ζ — about 65° at ζ=0.707 and about 76° at ζ=1. As a rule, aim for at least 45° and preferably around 60° for a stable design. This tool computes the phase margin directly from ζ.
Real-World Applications
Radio communications and tuners: Tuning a radio, TV, smartphone or Wi-Fi router is all done by a PLL. Using one crystal oscillator as the reference, switching the divider ratio N alone synthesises the frequency of the channel you want to receive. Applications that must switch channels quickly need a short lock time (a wide loop bandwidth), while preserving receiver sensitivity demands that output spurs be suppressed — so the bandwidth is designed carefully.
CPU and FPGA clock generation: A PLL is what turns the tens-of-MHz crystal on a motherboard into the GHz-class clock that runs a CPU core. A chip contains several PLLs, each supplying the frequency that a given block needs. If the jitter (clock wander) is large the logic can misbehave, so a low-phase-noise loop design directly governs quality.
Clock-data recovery (CDR): On the receive side of high-speed serial links (USB, PCI Express, SerDes), a PLL extracts the clock from the data signal itself. It locks its phase onto the transitions of the incoming bit stream so the data is sampled at the right instant. The balance between jitter tracking and noise rejection determines link quality.
Instruments, FM demodulation and motor control: The frequency source of a signal generator or spectrum analyser, the demodulator of an FM broadcast, the rotation sync of a brushless motor — wherever something must "lock its phase to a signal", a PLL is at work. The 2nd-order loop analysis behind this tool maps directly onto the first lock-time and stability estimate done in all of those designs.
Common Misconceptions and Pitfalls
The most common mistake is assuming that "a wider loop bandwidth is always better". A wider bandwidth does lock faster and suppresses VCO phase noise, but spurs on the reference and divider jitter pass straight through the loop and appear at the output within the band. Worse, if the loop bandwidth gets too close to the reference frequency, discrete sampling effects can make the loop itself unstable. The correct rule of thumb is to keep the loop bandwidth below one tenth of the reference frequency and search for the optimum that satisfies both the lock time and the output noise.
Next, the assumption that "lock time depends only on the damping ratio ζ". As t_lock ≈ 4/(ζ·ωn) shows, lock time is inversely proportional to the product of ζ and the natural frequency ωn. To make it faster while keeping ζ near 0.707 you must raise ωn — that is, widen the loop bandwidth. The real lock time is also affected by frequency pull-in (acquiring from a large initial frequency offset) and can be longer than the settling time predicted by a linear 2nd-order model. Treat the values here as a linear-region estimate.
Finally, the misconception that "raising the divider ratio N does not change the loop dynamics". The divider reduces the feedback-path gain by 1/N, so increasing N lowers the effective loop gain and shifts the natural frequency ωn and loop bandwidth. Real designs compensate for this N-dependence by adjusting the charge-pump current or loop-filter components. This tool uses a simplified model in which you enter the loop bandwidth directly, treating N and the loop dynamics independently — but in real design always account for the fact that changing N changes the bandwidth.
How to Use
Enter reference frequency (frefNum) between 1–100 MHz and division ratio (ndivNum) as integer 2–256 to set target output: f_out = fref × ndivNum.
Set loop bandwidth (loopBWNum) in kHz (typical 10–500 kHz for integer-N PLLs) and damping ratio zetaNum (0.5–2.0; use 0.707 for critical damping).
Click Simulate to compute settling time, overshoot, phase margin, and stability. Adjust parameters iteratively to minimize lock time while maintaining overshoot <20% and phase margin >45°.
Worked Example
Design a PLL synthesizing 2.4 GHz from a 24 MHz crystal: frefNum=24 MHz, ndivNum=100, loopBWNum=150 kHz, zetaNum=0.707. Simulator outputs: f_out=2400 MHz, ωn≈942 rad/s, lock time≈2.8 µs, overshoot≈4.2%, phase margin≈65°, verdict=Stable. This configuration suits GSM/CDMA RF transceiver frontends with tight frequency accuracy (±2.5 ppm).
Practical Notes
Higher loop bandwidth (e.g., 300 kHz vs. 50 kHz) reduces lock time but increases phase noise; balance depends on reference clock quality and channel bandwidth.
Underdamped PLL (zeta <0.707) speeds acquisition but risks >20% overshoot, causing momentary frequency deviation in hopping systems.
For fractional-N synthesis (e.g., LTE carriers), larger ndivNum values lower reference spurs but degrade loop stability; verify phase margin >50° before implementation.