A "via" that connects layer to layer in a printed circuit board carries a parasitic inductance that high-speed signals cannot ignore. Adjust the via length, diameter, signal frequency and the number of parallel vias to see the parasitic inductance and inductive reactance update in real time, and find a via design that preserves signal integrity.
Parameters
Via length h (board thickness)
mm
Thickness of the board the via passes through. 1.6 mm is a standard FR-4 board
Via diameter d
mm
Drilled hole diameter. Typical through-hole vias are 0.2–0.4 mm
Signal frequency f
GHz
Frequency being evaluated. For digital signals, the effective frequency of the edge
Parallel vias n
vias
Number of vias placed on the same current path — shows the via-stitching effect
Results
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Via inductance L (nH)
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Inductive reactance X_L (Ω)
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L with n in parallel (nH)
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Reactance with n in parallel (Ω)
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Aspect ratio h/d
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Reactance reduction (%)
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Via cross-section — current-flow animation
Current flows vertically through the via barrel connecting two copper layers. The via length h and diameter d are labelled, and when the parallel-via count is 2 or more, several barrels are drawn side by side.
Inductive reactance vs signal frequency f
Via inductance vs aspect ratio h/d
Theory & Key Formulas
$$L\approx\frac{\mu_0 h}{2\pi}\left[\ln\frac{4h}{d}+1\right],\qquad X_L=2\pi f L$$
Parasitic inductance L of a single barrel via and its inductive reactance X_L. h: via length, d: via diameter, f: frequency. The μ0/2π coefficient corresponds to about 0.2 nH/mm.
$$L_n=\frac{L}{n},\qquad X_n=\frac{X_L}{n}$$
With n vias in parallel on the same path, the combined inductance and inductive reactance fall to 1/n. Via inductance becomes a non-negligible signal-integrity concern above roughly 1 GHz.
What is a PCB Via's Inductance?
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A "via" is just a tiny hole that connects layer to layer in a circuit board, right? Why would a plain hole have any inductance?
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Good question. A via is a thin copper cylinder — a drilled hole plated with copper on its inner wall. Any conductor that carries current has a magnetic field around it, and "when the current changes, that field changes and produces a back-EMF" — that is exactly what inductance is. So however short a via is, as long as it is a path for current it always has a parasitic inductance. A typical 1.6 mm via comes in around 1 nH.
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1 nH looks like a tiny number. Does it still cause trouble?
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That is the key point. The inductance itself is small, but what bites you is the "inductive reactance X_L = 2πfL", which is directly proportional to frequency f. A 1 nH via is 0.6 Ω at 100 MHz — almost negligible. But it is about 31 Ω at 5 GHz and over 120 Ω at 20 GHz. When tens of ohms of series impedance suddenly cut into a 50 Ω transmission line, that cannot be ignored. Push the frequency slider on the left and watch the curve on the chart below.
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So the faster the signal, the more it matters. What actually happens because of that series reactance?
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The main problem is an "impedance discontinuity". On a trace carefully designed to a clean 50 Ω, the via creates a local spot where the impedance jumps up. Part of the signal reflects there and travels back, so the waveform rounds off, you get ringing, and insertion loss rises. In high-speed digital that closes the eye diagram and leads to bit errors; in RF the return loss degrades. It is better to think of a via not as a "small hole" but as a "small inductor".
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So how do you reduce that via inductance?
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There are three levers. First, "make it shorter". The formula L ≈ 0.2·h·(ln(4h/d)+1) shows L is roughly proportional to length h, so using a thinner board or trimming the unused stub with blind vias or back-drilling helps. Second, "make it fatter" — but d only appears inside the logarithm, so its effect is weak. And the most practical one is "paralleling": line up n vias and the combined inductance drops to L/n. Power and ground via stitching, or placing a return via next to a signal via, is exactly this principle. Increase the parallel-via count on the left and watch the reduction.
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If paralleling always helps, can't I just keep adding more and more vias?
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In theory it is L/n, but reality is not that simple. Vias placed close together share their magnetic fields and have "mutual inductance", so four vias rarely get all the way down to an ideal one-quarter. That is why vias you want to be effective should be spaced a little apart. Adding vias also eats board area and can break up signal layers. In practice "aim for a useful reduction with 2–4 vias and suppress mutual coupling by placement" is the realistic balance.
Frequently Asked Questions
The parasitic inductance of a single barrel (cylindrical) via is found from the approximation L ≈ 0.2·h·(ln(4h/d)+1) [nH], where h is the via length (board thickness) and d is the via diameter, both in mm, and ln is the natural logarithm. The 0.2 nH/mm coefficient comes from μ0/2π. For h=1.6mm and d=0.3mm, L ≈ 1.30 nH. Inductance is roughly proportional to length h and only logarithmic in diameter d, so shortening the via is by far the most effective lever.
Inductive reactance is X_L = 2πfL, which rises in direct proportion to frequency f. Even with L fixed, a 10× higher f gives 10× the reactance. A 1.3 nH via is about 0.8 Ω at 100 MHz — almost negligible — but about 41 Ω at 5 GHz and about 160 Ω at 20 GHz. This series reactance creates an impedance discontinuity in the transmission line, causing reflections, insertion loss and timing shifts, so via inductance becomes increasingly important as speed and frequency rise.
Placing n vias in parallel on the same current path drops the combined inductance, to first order, to L/n, and the inductive reactance to 1/n. Two vias give a 50% reduction, four vias 75%. Lining up several vias — "via stitching" or "via arrays" — is the standard technique for power and ground connections and for signal return paths. In practice mutual inductance between vias erodes the gain somewhat, so spacing the vias well apart is important.
Aspect ratio is the via length h divided by the via diameter d (h/d), and describes how slender the via is. Electrically, a larger aspect ratio (a more slender via) means more inductance. On the manufacturing side, plating solution cannot flow evenly into a very high aspect-ratio hole, so 8–10 is a common upper limit for volume production. From both the electrical and manufacturing point of view, vias should be "short and fat", and this tool lets you see the relationship between aspect ratio and inductance.
Real-World Applications
Layer transitions on high-speed digital boards: High-speed signals above a few Gbps — DDR memory, PCI Express, SerDes — pass through a via every time they change layers. The via's parasitic inductance produces a local impedance rise that closes the eye diagram. The standard practice is to place a ground via for the return current right next to the signal via to cut the loop inductance. Knowing the inductance of a single via with this tool tells you roughly at which frequency countermeasures become necessary.
Power distribution network (PDN): On the path that supplies power to an IC, via inductance is a major enemy that cancels out the effect of decoupling capacitors. The effective inductance of a capacitor includes not only its own ESL but also, in series, the inductance of the vias dropping from the pads down to the plane. To reduce this, designers assign several vias to one capacitor or place the via directly under the pad (via-in-pad).
Ground connections in RF and microwave circuits: When a transistor source or a stub in a microstrip circuit is dropped to the ground on the back of the board, series via inductance shifts the matching and affects gain and stability. In GHz-band amplifier design, grouping several ground vias together and optimizing via positions can make or break performance. The reduction ratio from parallel vias in this tool serves directly as a design guideline.
Via stitching for EMI and noise control: A "via fence / stitching" — many vias placed at equal spacing along board edges or signal-layer boundaries — ties ground planes together with low impedance and suppresses unwanted radiation and inter-layer noise coupling. Estimating the combined inductance from the per-via value and the count lets you verify a sensible via spacing (generally below 1/10 to 1/20 of the wavelength at the highest frequency).
Common Misconceptions and Pitfalls
The biggest misconception is "a via is just a connection point and is electrically transparent". In low-speed circuits you can treat a via as a point, but for a signal with a short rise time (i.e. a high effective frequency) a via is a clear lumped element of series inductance plus parasitic capacitance. This tool handles the series inductance of the barrel, but a real via also carries the parasitic capacitance formed by its pads and anti-pads, and the two together form a small LC network. For precise GHz-band design, the basic approach is to extract S-parameters with a 3D electromagnetic-field simulator (FEM / FDTD), not just an approximate formula.
Next, treating the coefficient and logarithmic term of the inductance formula as exact. The L ≈ 0.2·h·(ln(4h/d)+1) used here is one representative approximation for an isolated cylindrical conductor, and the coefficient and the exact form of the term vary slightly between references. The inductance of a real via is a "loop inductance" that depends strongly on where the return current flows (the position of adjacent ground vias), and differs from the self-inductance of an isolated via. Take this tool's numbers as a guide to orders of magnitude and trends, and finalize the design with simulation.
Finally, the misconception that "adding parallel vias always gets you down to L/n". Ideally n vias give 1/n, but vias placed close together share magnetic flux and have a positive mutual inductance. As a result, four vias do not reach an ideal quarter of the inductance — losing about 30% of the expected gain is common. To maximize the effect, the key mindset is to space the vias apart as much as possible and, more fundamentally, to shrink the loop area of the return current itself. Remember that in high-frequency design "shrink the loop" matters more than "add more vias".
How to Use
Enter via hole depth (h) in mm—typical range 0.5–3.0 mm for multilayer boards.
Enter via diameter (d) in mm—standard 0.3–0.8 mm for high-speed designs.
Specify signal frequency (f) in MHz or GHz to calculate inductive reactance X_L = 2πfL.
Set number of parallel vias (n) to model via stitching; reactance reduces inversely with n².
Click Calculate to display via inductance in nanohenries, reactance in ohms, aspect ratio h/d, and parallel reduction percentage.
Worked Example
PCB via connecting ground plane to power plane: h=1.2 mm, d=0.3 mm, f=2.5 GHz, n=1 single via. Calculated inductance L≈0.31 nH, inductive reactance X_L≈4.87 Ω. Adding four parallel vias (n=4) reduces reactance to ≈0.30 Ω and inductance to ≈0.078 nH per via, a 94% reactance reduction. Aspect ratio h/d=4.0 indicates good impedance control for 2.5 GHz DDR5 signaling.
Practical Notes
Via inductance dominates loop inductance in high-speed routing; minimize h/d ratio below 5:1 for sub-3 GHz digital and RF applications.
Parallel via stitching around signal vias (guard vias) reduces ground bounce and crosstalk—use 2–4 vias per signal via in 10+ Gbps designs.
Frequency-dependent reactance rises linearly; at 5 GHz, reactance quadruples from 1 GHz baseline, causing ringing and reflections if not impedance-matched.
Via diameter trade-off: smaller d reduces L but increases plating resistance and drilling cost; 0.4 mm balances performance and manufacturability for consumer electronics.