Switching Loss Analysis

Put simply, conduction loss is the loss that occurs steadily when the device is in the ON state. For a MOSFET, it's calculated as $R_{ds(on)} \times I_D^2$, and for an IGBT, it's $V_{CE(sat)} \times I_C$. It's like the power consumption of a light bulb that's constantly on.

On the other hand, switching loss occurs during the transient periods of turn-on and turn-off—that is, the "instant" when switching from ON to OFF or OFF to ON. During this moment, there is a period where voltage and current exist simultaneously, and the integral of their product becomes the switching energy.

Exactly. An ideal switch would switch instantaneously, resulting in zero loss, but actual MOSFETs and IGBTs have finite rise time $t_{rise}$ and fall time $t_{fall}$. For example, consider a SiC MOSFET operating at 400V/100A. Roughly $E_{sw} \approx 0.5 \, \text{mJ}$ of energy is converted to heat per switching event. If you switch this at 100kHz—

Yes, that's the essence of switching loss. The loss increases proportionally with frequency. That's why accurately predicting switching loss is incredibly important for thermal design in power electronics.

First, the energy consumed in one switching event is found by integrating the instantaneous power during the transient period:

Writing it separately for turn-on and turn-off:

And the switching power loss is the total switching energy per cycle multiplied by the switching frequency:

Datasheets list $E_{on}$ and $E_{off}$ under specific conditions (e.g., $V_{DS}=400\,\text{V}$, $I_D=20\,\text{A}$, $T_j=25\,^\circ\text{C}$). However, actual operating conditions differ, so scaling considering voltage, current, and temperature dependencies is necessary:

In practice, $k_v \approx 1.2 \sim 1.4$, $k_i \approx 0.8 \sim 1.0$, and the temperature coefficient $\alpha_T \approx 0.002 \sim 0.005 \, /\text{K}$ are good guidelines. For IGBTs, $E_{off}$ tends to be larger due to the influence of tail current.

Right. For SiC, $E_{sw}$ can increase by 20-30% at 125°C compared to 25°C. Overlooking this leads to accidents like "the simulation was fine, but the actual device had a thermal runaway."

It's helpful to understand turn-on by dividing it into four phases:

1. Gate Charging Period (Turn-on delay $t_{d(on)}$): Gate voltage rises to the threshold $V_{th}$. No current flows yet.
2. Current Rise Period: $V_{GS}$ exceeds $V_{th}$, and $i_D$ starts to rise. During this time, $v_{DS}$ still maintains a high voltage → voltage × current overlap occurs.
3. Miller Period (Plateau): $V_{GS}$ stagnates around the Miller voltage, and $v_{DS}$ drops sharply. The gate driver current is charging the gate-drain capacitance $C_{GD}$ (= Miller capacitance).
4. $v_{DS}$ Drop Completion: $v_{DS}$ settles to approximately $R_{ds(on)} \times I_D$, transitioning to the conduction state.

Turn-off is the reverse sequence, but for IGBTs, tail current (minority carrier recombination) is added, making $E_{off}$ prone to being larger. SiC MOSFETs are unipolar devices, so they have no tail current, and turn-off is dramatically faster.

Correct. Increasing the gate drive current $I_G$ speeds up the charging/discharging of the Miller capacitance, making $dv/dt$ steeper. However, if $dv/dt$ is too large, EMI noise issues arise, and lowering the gate resistance too much risks gate oscillation. This is the trade-off point in power electronics design.

The parasitic inductance $L_p$ of the power loop causes a voltage surge $v_{surge} = L_p \cdot \frac{dI}{dt}$ during turn-off. With the fast switching of SiC MOSFETs ($dI/dt > 5 \, \text{kA/}\mu\text{s}$), even just $10 \, \text{nH}$ of parasitic inductance results in:

A 50V voltage surge rides on top of $V_{DS}$. For a 650V-rated SiC MOSFET with $V_{DC}=400\,\text{V}$, that's 450V including the surge. Factoring in a safety margin, if you don't suppress the power loop inductance to below a few nH, you'll exceed the device's Safe Operating Area (SOA).

That's where FEM comes in. You model the 3D shape of the power module and perform electromagnetic field analysis including busbars, bonding wires, and substrate patterns. Extracting the parasitic inductance with tools like Ansys Q3D or the COMSOL AC/DC module and reflecting that value in circuit simulations to predict switching waveforms—this is the standard workflow in practice.

Comparing under the same 400V/100A conditions, it's roughly like this:

That's precisely the challenge. To leverage GaN's performance, you need to suppress the power loop inductance to below 1nH. That's why GaN devices are trending towards "GaN ICs" that integrate drive circuits on-chip, or ultra-small chip-scale packages. The era where electromagnetic field simulation of the package holds the key to device performance is here.

The Double Pulse Test (DPT) is an industry-standard test method for evaluating the switching characteristics of power devices. The circuit is very simple, consisting of a DC power supply + device + inductive load + freewheeling diode.

1. 1st Pulse: Turn the gate ON to ramp up the inductor current to the desired value $I_L$. Control the current value by adjusting the pulse width.
2. OFF Period: Turn the gate OFF → acquire the turn-off waveform. Current commutates to the FWD, and the inductor current is maintained almost constant.
3. 2nd Pulse: Turn the gate ON again after a short interval → acquire the turn-on waveform. Measure the instant when current re-commutates from the FWD to the device.

When reproducing DPT in circuit simulators like LTspice or PLECS, the important points are:

• Device Model: Use manufacturer-provided SPICE models or Level 3 nonlinear capacitance models. The voltage dependency of $C_{iss}$, $C_{oss}$, $C_{rss}$ is important.
• Parasitic Elements: Always include the power loop's $L_p$ (typically 5~30nH) and the gate loop's $L_g$ (typically 5~15nH).
• FWD Model: For Si PiN diodes, the reverse recovery parameters ($t_{rr}$, $Q_{rr}$) greatly affect $E_{on}$.
• Time Step: To sufficiently resolve the switching transient period (~100ns), a maximum time step of around 0.1ns is needed.

From the simulation waveform, obtain $v_{DS}(t)$ and $i_D(t)$, calculate the instantaneous power $p(t) = v_{DS}(t) \cdot i_D(t)$, and numerically integrate it over the switching period. In LTspice, you can calculate it automatically with the .meas command:

.meas TRAN Eon INTEG V(drain)*I(M1) FROM=t_on_start TO=t_on_end
.meas TRAN Eoff INTEG V(drain)*I(M1) FROM=t_off_start TO=t_off_end

Yes. This is called "Mixed-mode simulation," a method that simultaneously solves the semiconductor physics of the device (drift-diffusion equations, Poisson's equation) with the circuit equations. It can be done with Sentaurus Device or Silvaco Atlas.

In the design phase of new device structures—for example, optimizing trench gate shapes or designing field plates—SPICE models don't exist yet, so device physics simulation becomes the only predictive tool.

In such cases, the semiconductor physics simulator outputs the device's internal charge distribution and electric field, which is fed back into the circuit simulator. The feedback loop repeats until convergence, yielding accurate transient waveforms that capture the physics of the device interior.