Switching Loss Analysis
Theory and Physics
Switching Loss vs. Conduction Loss
Professor, what's the difference between switching loss and conduction loss? The word "loss" comes up so much in power electronics class, my head is spinning...
Put simply, conduction loss is the loss that occurs steadily when the device is in the ON state. For a MOSFET, it's calculated as $R_{ds(on)} \times I_D^2$, and for an IGBT, it's $V_{CE(sat)} \times I_C$. It's like the power consumption of a light bulb that's constantly on.
On the other hand, switching loss occurs during the transient periods of turn-on and turn-off—that is, the "instant" when switching from ON to OFF or OFF to ON. During this moment, there is a period where voltage and current exist simultaneously, and the integral of their product becomes the switching energy.
Huh? If it's either ON or OFF, one of them is zero, so the loss should be zero, right? So the problem only occurs during that switching instant?
Exactly. An ideal switch would switch instantaneously, resulting in zero loss, but actual MOSFETs and IGBTs have finite rise time $t_{rise}$ and fall time $t_{fall}$. For example, consider a SiC MOSFET operating at 400V/100A. Roughly $E_{sw} \approx 0.5 \, \text{mJ}$ of energy is converted to heat per switching event. If you switch this at 100kHz—
Let's see... $0.5 \, \text{mJ} \times 100{,}000 = 50 \, \text{W}$! Even though a single event is small, at high frequencies it really adds up!
Yes, that's the essence of switching loss. The loss increases proportionally with frequency. That's why accurately predicting switching loss is incredibly important for thermal design in power electronics.
Formulation of Switching Energy
Please teach me the proper formula for switching loss!
First, the energy consumed in one switching event is found by integrating the instantaneous power during the transient period:
Writing it separately for turn-on and turn-off:
And the switching power loss is the total switching energy per cycle multiplied by the switching frequency:
I see, that formula is intuitive. In datasheets, how are $E_{on}$ and $E_{off}$ written?
Datasheets list $E_{on}$ and $E_{off}$ under specific conditions (e.g., $V_{DS}=400\,\text{V}$, $I_D=20\,\text{A}$, $T_j=25\,^\circ\text{C}$). However, actual operating conditions differ, so scaling considering voltage, current, and temperature dependencies is necessary:
In practice, $k_v \approx 1.2 \sim 1.4$, $k_i \approx 0.8 \sim 1.0$, and the temperature coefficient $\alpha_T \approx 0.002 \sim 0.005 \, /\text{K}$ are good guidelines. For IGBTs, $E_{off}$ tends to be larger due to the influence of tail current.
So you can't just use the 25°C value from the datasheet as-is. If the actual junction temperature is over 100°C, it could be quite off...
Right. For SiC, $E_{sw}$ can increase by 20-30% at 125°C compared to 25°C. Overlooking this leads to accidents like "the simulation was fine, but the actual device had a thermal runaway."
Turn-On/Turn-Off Mechanism
What exactly happens during turn-on and turn-off? What does it look like on a waveform?
It's helpful to understand turn-on by dividing it into four phases:
- Gate Charging Period (Turn-on delay $t_{d(on)}$): Gate voltage rises to the threshold $V_{th}$. No current flows yet.
- Current Rise Period: $V_{GS}$ exceeds $V_{th}$, and $i_D$ starts to rise. During this time, $v_{DS}$ still maintains a high voltage → voltage × current overlap occurs.
- Miller Period (Plateau): $V_{GS}$ stagnates around the Miller voltage, and $v_{DS}$ drops sharply. The gate driver current is charging the gate-drain capacitance $C_{GD}$ (= Miller capacitance).
- $v_{DS}$ Drop Completion: $v_{DS}$ settles to approximately $R_{ds(on)} \times I_D$, transitioning to the conduction state.
Turn-off is the reverse sequence, but for IGBTs, tail current (minority carrier recombination) is added, making $E_{off}$ prone to being larger. SiC MOSFETs are unipolar devices, so they have no tail current, and turn-off is dramatically faster.
So a longer Miller period means greater loss. Does strengthening the gate driver shorten the Miller period?
Correct. Increasing the gate drive current $I_G$ speeds up the charging/discharging of the Miller capacitance, making $dv/dt$ steeper. However, if $dv/dt$ is too large, EMI noise issues arise, and lowering the gate resistance too much risks gate oscillation. This is the trade-off point in power electronics design.
Effect of Parasitic Inductance
A senior told me, "Lower the power loop inductance with your life," but why is it so important?
The parasitic inductance $L_p$ of the power loop causes a voltage surge $v_{surge} = L_p \cdot \frac{dI}{dt}$ during turn-off. With the fast switching of SiC MOSFETs ($dI/dt > 5 \, \text{kA/}\mu\text{s}$), even just $10 \, \text{nH}$ of parasitic inductance results in:
A 50V voltage surge rides on top of $V_{DS}$. For a 650V-rated SiC MOSFET with $V_{DC}=400\,\text{V}$, that's 450V including the surge. Factoring in a safety margin, if you don't suppress the power loop inductance to below a few nH, you'll exceed the device's Safe Operating Area (SOA).
A few nH! How do you evaluate such tiny inductance?
That's where FEM comes in. You model the 3D shape of the power module and perform electromagnetic field analysis including busbars, bonding wires, and substrate patterns. Extracting the parasitic inductance with tools like Ansys Q3D or the COMSOL AC/DC module and reflecting that value in circuit simulations to predict switching waveforms—this is the standard workflow in practice.
Advantage of SiC/GaN Wide Bandgap Devices
I hear SiC and GaN are advantageous for switching loss, but how different are they specifically?
Comparing under the same 400V/100A conditions, it's roughly like this:
| Parameter | Si IGBT | SiC MOSFET | GaN HEMT (650V) |
|---|---|---|---|
| $E_{on}$ [mJ] | 2.0〜5.0 | 0.2〜0.5 | 0.05〜0.2 |
| $E_{off}$ [mJ] | 1.5〜3.0 | 0.1〜0.3 | 0.02〜0.1 |
| $t_{rise}$ [ns] | 50〜200 | 10〜30 | 2〜10 |
| $t_{fall}$ [ns] | 100〜500 | 10〜40 | 2〜15 |
| Practical $f_{sw}$ Upper Limit | 20〜50kHz | 50〜200kHz | 100kHz〜1MHz |
GaN is amazing... It's another order of magnitude faster even compared to SiC. But doesn't that make the effect of parasitic inductance even greater?
That's precisely the challenge. To leverage GaN's performance, you need to suppress the power loop inductance to below 1nH. That's why GaN devices are trending towards "GaN ICs" that integrate drive circuits on-chip, or ultra-small chip-scale packages. The era where electromagnetic field simulation of the package holds the key to device performance is here.
Why Switching Loss is "Proportional to Frequency"
Switching loss is proportional to $P_{sw} = E_{sw} \times f_{sw}$. Because $E_{sw}$ of energy inevitably turns into heat per ON/OFF cycle, if you do it once per second, it's $E_{sw}$ watts; if you do it 100 times, it's $100 E_{sw}$ watts. On the other hand, increasing $f_{sw}$ allows inductors and capacitors to be miniaturized (inductance is roughly inversely proportional to $f_{sw}$). "Faster switching makes passive components smaller but increases loss"—this trade-off is at the core of power converter design. SiC/GaN pushes the equilibrium point towards higher frequencies by reducing $E_{sw}$ itself. That's the essence behind the dramatic miniaturization of equipment.
Triangular Approximation and Exact Integration of Switching Energy
For rough estimates at the datasheet level, the turn-on/turn-off waveforms can be approximated as triangles and calculated as follows:
$$ P_{sw,approx} = \frac{1}{2} V_{DS} \cdot I_D \cdot (t_{rise} + t_{fall}) \cdot f_{sw} $$However, this is a simplified formula that ignores the simultaneous change of voltage and current during the Miller period, the reverse recovery current $I_{rr}$ of the diode, and ringing due to parasitic inductance. The accurate $E_{sw}$ is:
$$ E_{sw} = \int_{t_0}^{t_0 + t_{sw}} v_{DS}(t) \cdot i_D(t) \, dt $$To correctly evaluate this integral, simulation of the switching transient waveform is essential. In actual measurements, it's obtained by numerical integration from the waveform of a double pulse test.
Effect of Reverse Recovery Current $I_{rr}$
When using a Si PiN diode as the freewheeling diode (FWD), a reverse recovery current $I_{rr}$ superimposes on the MOSFET/IGBT during turn-on. This increases the effective turn-on current to $I_D + I_{rr}$, significantly worsening $E_{on}$. Using a SiC SBD makes reverse recovery nearly zero, allowing $E_{on}$ to be greatly reduced.
$$ E_{on,total} = \underbrace{E_{on,device}}_{\text{MOSFET/IGBT}} + \underbrace{E_{rr,diode}}_{\text{FWD Reverse Recovery Loss}} $$Dimensional Analysis and Unit System
| Variable | SI Unit | Typical Value (SiC 1200V/100A) |
|---|---|---|
| Switching Energy $E_{sw}$ | J (Joule) | 0.3〜2.0 mJ |
| Switching Frequency $f_{sw}$ | Hz | 10〜200 kHz |
| Switching Power Loss $P_{sw}$ | W (Watt) | 10〜200 W |
| Rise Time $t_{rise}$ | s (second) | 10〜50 ns |
| Parasitic Inductance $L_p$ | H (Henry) | 1〜50 nH |
| Gate-Drain Capacitance $C_{GD}$ | F (Farad) | 5〜50 pF |
Numerical Methods and Implementation
Double Pulse Test Simulation
I often hear about the "Double Pulse Test." What kind of test is it? Can it be reproduced in simulation too?
The Double Pulse Test (DPT) is an industry-standard test method for evaluating the switching characteristics of power devices. The circuit is very simple, consisting of a DC power supply + device + inductive load + freewheeling diode.
- 1st Pulse: Turn the gate ON to ramp up the inductor current to the desired value $I_L$. Control the current value by adjusting the pulse width.
- OFF Period: Turn the gate OFF → acquire the turn-off waveform. Current commutates to the FWD, and the inductor current is maintained almost constant.
- 2nd Pulse: Turn the gate ON again after a short interval → acquire the turn-on waveform. Measure the instant when current re-commutates from the FWD to the device.
I see, you create the current with the first pulse and capture the switching characteristics with the second. How is it modeled in simulation?
When reproducing DPT in circuit simulators like LTspice or PLECS, the important points are:
- Device Model: Use manufacturer-provided SPICE models or Level 3 nonlinear capacitance models. The voltage dependency of $C_{iss}$, $C_{oss}$, $C_{rss}$ is important.
- Parasitic Elements: Always include the power loop's $L_p$ (typically 5〜30nH) and the gate loop's $L_g$ (typically 5〜15nH).
- FWD Model: For Si PiN diodes, the reverse recovery parameters ($t_{rr}$, $Q_{rr}$) greatly affect $E_{on}$.
- Time Step: To sufficiently resolve the switching transient period (~100ns), a maximum time step of around 0.1ns is needed.
A 0.1ns time step! That's quite fine. How do you calculate the switching energy from the simulation results?
From the simulation waveform, obtain $v_{DS}(t)$ and $i_D(t)$, calculate the instantaneous power $p(t) = v_{DS}(t) \cdot i_D(t)$, and numerically integrate it over the switching period. In LTspice, you can calculate it automatically with the .meas command:
.meas TRAN Eon INTEG V(drain)*I(M1) FROM=t_on_start TO=t_on_end
.meas TRAN Eoff INTEG V(drain)*I(M1) FROM=t_off_start TO=t_off_endCircuit-Device Co-Simulation
Are there cases where you couple circuit simulation with device-internal physical simulation, not just circuit simulation alone?
Yes. This is called "Mixed-mode simulation," a method that simultaneously solves the semiconductor physics of the device (drift-diffusion equations, Poisson's equation) with the circuit equations. It can be done with Sentaurus Device or Silvaco Atlas.
In the design phase of new device structures—for example, optimizing trench gate shapes or designing field plates—SPICE models don't exist yet, so device physics simulation becomes the only predictive tool.
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