Parasitic Inductance Analysis — Loop Inductance Extraction and Reduction Design in Power Electronics

That "mere nH" can be fatal. The key is the magnitude of di/dt (rate of change of current). In recent SiC MOSFET switching, $di/dt$ reaches 10 A/ns. At that time, even just 10 nH of parasitic inductance causes:

That is, a 100 V surge voltage is generated. For an 800 V rated SiC MOSFET with a bus voltage of 600 V, 600 + 100 = 700 V is barely within limits. If the parasitic inductance is 20 nH, a 200 V surge would exceed the rating and destroy the device.

Si IGBT's di/dt is at most about 1 A/ns. Even with 10 nH, only a 10 V surge occurs. So in the past, it was okay with "even if the wiring is a bit long, it's probably fine." High-speed switching of SiC/GaN has made di/dt more than 10 times higher, so the impact of parasitic inductance has suddenly become apparent. Extracting and minimizing the inductance of current loops formed by busbar or PCB conductor layouts using 3D FEM or PEEC methods has become essential in today's design.

Wherever current flows, a magnetic field is generated. The magnetic field storing energy means inductance exists there. Specifically:

• Busbar — A large distance between DC+ and DC- conductors increases loop area, resulting in tens of nH
• Inside power modules — About 2–5 nH per bonding wire
• PCB vias and traces — About 0.5–1 nH per via
• Decoupling capacitor leads — ESL (Equivalent Series Inductance) of 1–5 nH

When these sum to tens of nH, it becomes a serious surge voltage issue for SiC. Moreover, parasitic inductance is determined by geometric arrangement, so it doesn't appear in schematics. That's why 3D electromagnetic field analysis is necessary.

First, let's organize three basic equations.

1. Surge Voltage (at turn-off)

Here $V_{DC}$ is the bus voltage, $L_{loop}$ is the total inductance of the switching loop, and $V_{diode}$ is the forward voltage drop of the diode.

2. Stored Magnetic Energy

This energy is absorbed by snubber circuits or the device's parasitic capacitance. If too large, ringing (oscillation) prolongs and becomes a source of EMI.

3. Ringing Frequency

$C_{oss}$ is the device's output capacitance. LC resonance between $L_{loop}$ and $C_{oss}$ causes high-frequency ringing in the tens to hundreds of MHz after switching. This very often causes EMI standard violations.

Exactly. Therefore, in power electronics design, "how to minimize loop inductance" is the starting point for everything. Target values are:

• Si IGBT: $L_{loop}$ < 50 nH is generally OK
• SiC MOSFET: $L_{loop}$ < 10 nH is the target, ideally below 5 nH
• GaN HEMT: $L_{loop}$ < 2 nH, assuming chip-scale packages

This is the most important concept in parasitic inductance analysis, so understand it well.

Loop inductance is a physical quantity defined for the entire closed circuit, the "real" inductance measurable with a VNA or impedance analyzer:

On the other hand, partial inductance is a concept proposed by Ruehli in 1972, a mathematical tool to "attribute" inductance to individual conductor segments:

And loop inductance is calculated from partial inductance as follows:

The closer the forward and return paths are, the larger $M_{p,ij}$ becomes, and $L_{loop}$ becomes smaller. This is the mathematical explanation for why "bringing conductors closer reduces inductance."

Perfect understanding. Laminated busbars have a structure where two copper plates 0.5–2 mm thick are sandwiched with an insulating film, with a spacing of only 0.1–0.5 mm between forward and return paths. The narrower the spacing, the closer $M_{p,ij}$ gets to $L_{p,ii}$, so $L_{loop}$ dramatically decreases. What was 30–50 nH with discrete busbars can be reduced to 3–5 nH with laminated busbars.

Yes. The PEEC (Partial Element Equivalent Circuit) method is a technique proposed by Ruehli simultaneously with the concept of partial inductance, and it's the standard method for parasitic inductance extraction.

The basic idea is:

1. Divide conductors into small segments (cells)
2. Calculate the self partial inductance $L_p$ and resistance $R$ of each segment
3. Calculate the mutual partial inductance $M_p$ between segments
4. If dielectrics are present, also calculate the capacitance coefficients (partial capacitance $C_p$)
5. Assemble these into an RLC equivalent circuit

The PEEC equation between conductor segments $i$ and $j$ is:

In matrix form:

$\mathbf{L}_p$ becomes a dense matrix (full matrix) of partial inductance, which is a computational bottleneck, but a major advantage is that since only conductors are discretized, meshing of the air region is not required.

Yes, that's the biggest strength of the PEEC method. When analyzing busbars and bonding wires of an entire power module, FEM would require millions of elements in the air region, but the PEEC method only needs tens of thousands of cells for the conductors alone. However, dense matrix operations require $O(N^2)$ memory and $O(N^3)$ computation time, so for large-scale problems, acceleration using FMM (Fast Multipole Method) is essential.

FEM excels when there are nonlinear materials (B-H curve of iron cores) or complex geometries. For busbars with magnetic shields or power modules with built-in ferrite cores, FEM is the only choice.

The formulation uses the vector potential $\mathbf{A}$. To automatically satisfy magnetic flux conservation $\nabla \cdot \mathbf{B} = 0$, we set $\mathbf{B} = \nabla \times \mathbf{A}$, and from Ampere's law:

Here $\mathbf{J}_s$ is the external current source, and the second term on the right is the eddy current term. Assuming time-harmonic (sinusoidal) conditions, $\partial/\partial t \to j\omega$ gives the frequency-domain formulation.

Discretizing with edge elements (Nedelec elements) yields:

$\mathbf{K}$ is the stiffness matrix ($\nabla \times$ term), $\mathbf{M}$ is the mass matrix (eddy current term), and $\mathbf{a}$ is the degree-of-freedom vector on edges.

There are mainly two methods:

Energy method (most common):

Flux linkage method:

The energy method involves a volume integral, so it calculates the magnetic field energy of the entire domain including the air region. Therefore, if the air region mesh is too coarse, the result becomes inaccurate. This is the most important point to note when extracting inductance with FEM.

The basic approach is to divide conductors into rectangular volume filaments. Uniform current density is assumed in each cell, and partial inductance between cells is calculated by numerical integration of the Neumann formula.

Specifically, the mutual partial inductance between cell $i$ (volume $V_i$) and cell $j$ (volume $V_j$) is:

$a_i$, $a_j$ are the cross-sectional areas of each cell, and $\hat{\mathbf{l}}$ is the unit vector in the current direction.

This double volume integral can be evaluated quickly using the Graver formula or Hoer-Love formula when an analytical solution exists (e.g., rectangular cells with parallel axes). For arbitrary shapes, Gaussian quadrature is used.

Yes. Memory is $O(N^2)$, and LU decomposition computational complexity is $O(N^3)$. For $N = 10^5$ (100k cells), $10^{10}$ memory is needed, which is practically impossible. Therefore, the following acceleration techniques are used in tools like Ansys Q3D:

The steps for the FEM energy method are as follows:

1. Model Creation: 3D model of conductors + air region. Ensure the air region is 5–10 times the size of the conductors.
2. Excitation Condition: Apply a known current $I_0$ to the target loop.
3. Solve: Calculate the magnetic field $\mathbf{B}$.
4. Post-processing: Perform volume integration of the magnetic energy over the entire domain.

For mutual inductance, two calculations are needed:

Here $L_{12}$ is the inductance when current flows simultaneously in loop 1 and loop 2, and $L_1$, $L_2$ are the individual inductances.