WBG Device (SiC/GaN) Simulation
Theory: the breakdown–on-resistance trade-off
Overview
I've heard SiC MOSFETs are far smaller than Si devices of the same voltage rating. Why?
A power device blocks high voltage when off in its drift layer, which must be thick and lightly doped enough that the field stays below the material's critical field. When on, current must cross this thick, lightly doped layer, so resistance is high. SiC and GaN have critical fields about ten times silicon's, so for the same rating the layer can be about a tenth as thick and about sixty times more heavily doped. Together these make resistance fall with the cube of critical field. Baliga's limit expresses this and is the first guide in choosing a material.
Baliga's limit
BV is breakdown voltage, ε permittivity, μ_n electron mobility, E_c critical field, W_D drift thickness and N_D doping. Properties: Si (εr 11.7, mobility 1,350 cm²/Vs, 0.3 MV/cm), 4H-SiC (9.7, 900, 2.5 MV/cm), GaN (9.0, 1,200, 3.3 MV/cm).
Baliga's figure of merit
In 1982 Baliga proposed ε·μ·E_c³ as a figure of merit for comparing power semiconductor materials; drift-resistance limits scale inversely with it. Silicon power devices dominated then, but the figure showed SiC and GaN to be fundamentally far superior. Crystal quality and MOS-interface problems delayed practical use, but in the 2010s SiC MOSFETs and GaN transistors entered volume production, greatly improving efficiency in EVs and power supplies.
Worked examples
Example 1: drift-layer limits by voltage rating
| Rating | Material | Specific resistance (mΩ·cm²) | Drift thickness | Doping (cm⁻³) |
|---|---|---|---|---|
| 650 V | Si | 44.8 | 43 μm | 4.5×10¹⁴ |
| 650 V | 4H-SiC | 0.14 | 5.2 μm | 2.6×10¹⁶ |
| 650 V | GaN | 0.049 | 3.9 μm | 4.2×10¹⁶ |
| 1,200 V | Si | 153 | 80 μm | 2.4×10¹⁴ |
| 1,200 V | 4H-SiC | 0.48 | 9.6 μm | 1.4×10¹⁶ |
| 1,200 V | GaN | 0.17 | 7.3 μm | 2.3×10¹⁶ |
| 3,300 V | 4H-SiC | 3.6 | 26 μm | 5.1×10¹⁵ |
Example 2: area for a 20 mΩ, 1,200 V device (drift-limited)
| Material | Area | Side | Figure of merit vs Si |
|---|---|---|---|
| Si | 7.63 cm² | 27.6 mm | 1 |
| 4H-SiC | 0.024 cm² | 1.54 mm | 320 |
| GaN | 0.0084 cm² | 0.92 mm | 910 |
GaN has the lower limit, so why is SiC more common at 1,200 V?
The limit expresses ideal material performance; real devices are set by structure and manufacturing. Most GaN transistors are lateral, with thin GaN grown on substrates such as silicon and current flowing along the surface. Higher voltage needs wider electrode spacing, eroding the area advantage, and thick low-defect GaN is hard to grow. SiC allows vertical devices with thick drift layers on native substrates, suiting high voltage and large current. Hence GaN dominates fast supplies up to 650 V and SiC automotive and industrial use at 1,200 V and above. Real SiC MOSFETs at 1,200 V reach several times the limit once channel and substrate resistance are added; device simulation breaks resistance down to decide what to improve.
Device simulation workflow
- Use Baliga's formula to estimate drift thickness and doping for the rating.
- Build the device cross-section in TCAD and solve Poisson and continuity equations.
- Include material-specific models such as SiC interface traps and incomplete ionisation.
- Suppress edge field crowding with termination and confirm breakdown.
- Calibrate parameters against measured prototype characteristics.
“Breakdown fell short of calculation”
A 1,200 V SiC diode prototype had ample margin in 1D drift calculations, yet broke down at only about 900 V. TCAD including the device edge showed field crowding at the electrode edge, which failed first. Adding a field-grading termination (guard rings) and re-simulating, the redesigned prototype exceeded 1,300 V. 1D formulas describe only the active centre, so edge design must be checked by simulation.
Common mistakes
Mistakes and fixes
| Mistake | Effect | Fix |
|---|---|---|
| Treating the limit as a real device | Resistance underestimated | Add channel and substrate |
| 1D-only breakdown design | Edge breakdown | Analyse termination |
| Reusing Si models | Characteristics mismatch | Material-specific models |
| Ignoring temperature | Shifts when hot | Simulate over temperature |
| Ignoring incomplete ionisation | Wrong carrier density | Include for SiC |
I'd like to learn related topics.
Related pages include gate driver design, power device thermal design, power module packaging, EMI from switching and parasitic inductance.
Related Topics
Experience the theory firsthand with the interactive simulator for this field
All Simulators