Differential Signaling

Simply put, it's because differential can cancel out common-mode noise. Signals with opposite phases are sent on two conductors, and the receiver subtracts them. External noise affects both lines equally, so it gets canceled out during subtraction.

Good observation. Actually, differential signaling has another major benefit: EMI (Electromagnetic Interference) reduction. Since currents with opposite phases flow in close proximity, their magnetic fields cancel each other out at a distance, reducing radiated noise. For ultra-high-speed transmission like USB 3.2 at 5 Gbps or PCIe 5.0 at 32 GT/s, single-ended signaling can't pass EMC regulations.

Exactly. CMRR (Common-Mode Rejection Ratio) can achieve around 60-80 dB in actual measurements. That means common-mode noise can be suppressed to 1/1000th to 1/10,000th. This is the decisive difference from single-ended.

When analyzing two coupled transmission lines, the signals are decomposed into two independent modes. Odd Mode is the state where the two lines are driven with opposite phases, and the symmetry plane becomes a virtual ground. Even Mode is the state where the two lines are driven with the same phase, and the symmetry plane becomes an open boundary.

Yes. This is the core of differential signal design. Differential impedance $Z_{diff}$ and common-mode impedance $Z_{common}$ can be directly derived from odd-mode impedance $Z_{odd}$ and even-mode impedance $Z_{even}$:

Correct! In FEM analysis, we solve the cross-section of coupled microstrips to first calculate $Z_{odd}$ and $Z_{even}$. Once these two are known, the differential characteristics are completely determined.

The coupling coefficient $k$ indicates how electromagnetically coupled the two lines are. If the uncoupled single-line impedance is $Z_0$, then:

Exactly. For example, when $k = 0.1$ and $Z_0 = 50\Omega$, then $Z_{diff} = 2 \times 50 \times 0.9 = 90\Omega$. That's exactly the USB specification value. Narrowing the pair spacing increases $k$ and lowers $Z_{diff}$, so in PCB design, impedance is adjusted using both trace width and pair spacing.

Sharp observation. The coupling *within* a differential pair is intentional and not a problem. The issue is coupling with *another* adjacent differential pair—that is, pair-to-pair crosstalk. To suppress this, a basic rule is to maintain a spacing between pairs of at least three times the intra-pair spacing (the so-called 3W rule).

Common-mode components become the main culprit for EMI radiation. Depending on the standard, a typical target is $S_{cd21} < -20\text{dB}$. PCIe 5.0 requires it to be below $-26\text{dB}$. Checking this value with FEM or S-parameter analysis is standard practice.

Summarizing the differential impedance requirements for major high-speed serial standards:

Right. That's why precise impedance calculation using FEM analysis, including the PCB stack-up (layer configuration), trace width, pair spacing, and even solder resist thickness, is essential. "Roughly 90Ω" doesn't cut it at this level.

Approximate the unknown quantity using shape functions $N_i$:

This can be expressed mathematically like this.

This can be expressed mathematically like this.

Discretizing the governing equations of the continuum yields the following system of algebraic equations:

Here, $[K]$ is the global stiffness matrix (or equivalent system matrix), $\{u\}$ is the vector of unknown nodal variables, and $\{F\}$ is the external force vector.

• Full Integration: Integrates all terms accurately. Tends to overestimate stiffness (Locking).
• Reduced Integration: Reduces the number of integration points. Improves computational efficiency but risks hourglass mode occurrence.
• Selective Reduced Integration (B-bar Method): Separates and integrates volumetric and deviatoric terms separately. Avoids locking.

• h-refinement: Refine the mesh (reduce element size h) to improve accuracy.
• p-refinemen