Why does PCB routing need impedance control?

As edges get faster, traces act not as simple wires but as transmission lines with a defined characteristic impedance. Where impedance changes along or at the end of a trace, part of the signal reflects, distorting waveforms and causing malfunctions. Trace width, dielectric thickness and permittivity set the impedance, so they're controlled.

What trace width gives 50 Ω?

On FR-4 (relative permittivity 4.3) with 0.2 mm between the surface trace and its ground plane, the Hammerstad–Jensen formula gives about 0.39 mm. A 0.2 mm trace is 72 Ω and 0.5 mm is 43 Ω. Effective permittivity is 3.27, so signals travel at about 6.0 ps per mm (153 ps per inch).

At what length do reflections matter?

Compare rise time with the trace's round-trip delay. If the round trip is shorter than the rise time, reflections are buried in the edge. For this line the guide is about 83 mm at 1 ns rise time, 17 mm at 200 ps and 4 mm at 50 ps; longer traces need termination.

SI-Compliant PCB Design — Stackup, Impedance Control, and Wiring Topology Electromagnetic Field Simulation

Category: Electromagnetic Analysis – Signal Integrity | Revised 2026-10-01

SI-aware PCB design simulation showing stackup cross-section with impedance-controlled differential pairs and return path current distribution

SI-Compliant PCB Design: Impedance-controlled stackup cross-section and electromagnetic field distribution in differential pair routing

Theory: traces are transmission lines

Overview

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Do signals distort on a board because traces are too long?

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It depends not just on length but on how it compares with edge speed. If the signal changes more slowly than a round trip along the trace, the whole trace sits at nearly the same voltage and behaves as a wire. With faster edges, once the round trip takes longer, the trace becomes a transmission line and the signal travels as a wave that reflects wherever characteristic impedance changes. High-speed board design therefore keeps impedance uniform (often 50 Ω), matches impedance at the ends (termination) and checks whether lengths are short enough for reflections not to matter. Characteristic impedance follows from trace width, dielectric thickness and permittivity.

Microstrip characteristic impedance

$$ Z_0 = \frac{120\pi}{\sqrt{\varepsilon_{eff}}\left[\dfrac{w}{h} + 1.393 + 0.667\ln\!\left(\dfrac{w}{h} + 1.444\right)\right]},\quad \varepsilon_{eff} = \frac{\varepsilon_r + 1}{2} + \frac{\varepsilon_r - 1}{2}\left(1 + \frac{12h}{w}\right)^{-1/2}\quad (w/h \ge 1) $$

Hammerstad–Jensen formula (conductor thickness neglected). w is trace width and h dielectric thickness; a different form applies for w/h < 1.

Delay, critical length and reflection coefficient

$$ t_{pd} = \frac{\sqrt{\varepsilon_{eff}}}{c},\qquad l_{crit} \approx \frac{t_r}{2\,t_{pd}},\qquad \Gamma = \frac{Z_L - Z_0}{Z_L + Z_0} $$

t_r is rise time. Beyond l_crit, where the round-trip delay exceeds t_r, reflections appear as steps in the waveform.

Coffee Break Trivia

From telegraphy to high-speed digital

Transmission-line theory began with the telegrapher's equations developed in the 19th century by Heaviside and others to solve signal smearing on undersea telegraph cables. For a long time it concerned communications and broadcast engineers, but as digital rise times shrank to nanoseconds and then picoseconds, the same theory became necessary for board traces a few centimetres long. Today it's normal to compute characteristic impedance and set trace widths from the moment the board stackup is defined.

Worked examples

Example 1: trace width and impedance (FR-4, εr 4.3, 0.2 mm dielectric)

Width	Impedance	Effective εr
0.20 mm	71.8 Ω	3.11
0.30 mm	58.3 Ω	3.20
0.392 mm	50.0 Ω	3.27
0.50 mm	42.9 Ω	3.34

Delay of the 50 Ω line is 6.03 ps/mm (153 ps per inch).

Example 2: rise time and the length where reflections matter

Rise time	Critical length (round trip = t_r)	Stricter rule (t_r/6)
1 ns	82.9 mm	27.6 mm
200 ps	16.6 mm	5.5 mm
50 ps	4.1 mm	1.4 mm

Example 3: 25 Ω driver, 50 Ω line, unterminated load (1 V step)

Arrival	Load voltage
1st	1.333 V
2nd	0.889 V
3rd	1.037 V
4th	0.988 V
5th	1.004 V

Source reflection coefficient is −1/3 and the open load +1. Sections of 40, 60 and 75 Ω in a 50 Ω line give reflection coefficients of −0.11, +0.09 and +0.20.

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The load overshoots by 33% and rings several times before settling.

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An unterminated load doubles and reflects the voltage, which returns to the driver where part reflects again. With the 25 Ω driver mismatched to the 50 Ω line, each round trip returns a wave multiplied by −1/3. Overshoot can exceed the receiver's voltage rating, and ringback can cross thresholds and cause errors. A simple fix is series termination: a 25 Ω resistor right after the driver matches the source to 50 Ω. A half-amplitude wave then launches, doubles at the load to exactly 1 V, and the returning wave is absorbed at the source, stopping the ringing. For traces with multiple loads, parallel termination with a 50 Ω resistor at the far end is used.

Design and analysis workflow

Find critical length from rise time and identify traces to treat as transmission lines.
Define the stackup and compute widths for target impedance.
Choose termination to suit driver and load topology.
Evaluate impedance discontinuities such as vias and connectors with field solvers.
Measure prototypes with TDR to check impedance variation.

Coffee Break Trivia

“Worked in prototype, failed in production”

A board worked in prototype, but some production units had communication errors. The production fab's dielectric was thinner than the prototype's, giving about 42 Ω against a 50 Ω design. Mismatch with the termination resistor increased reflections, and a waveform with little margin crossed the threshold. Specifying controlled impedance (±10%) to the fab and requiring TDR test reports eliminated the errors.

Common mistakes

Mistakes and fixes

Mistake	Effect	Fix
Judging by clock frequency only	Fast edges missed	Judge by rise time
Uncontrolled dielectric thickness	Impedance drifts	Specify controlled impedance
Long unterminated traces	Overshoot and ringing	Series or parallel termination
Broken return path	Impedance jump	Continuous ground plane
Ignoring vias	Reflections at speed	Evaluate by field solver

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I'd like to learn related topics.

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Related pages include impedance matching, crosstalk, eye diagrams, power integrity and differential signalling.

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