Via Modeling—A Method for SI Analysis of High-Speed PCBs
Theory and Physics
Via Structure and High-Frequency Issues
Professor, a via is just a hole in the substrate, right? If electricity can pass through, why do we need electromagnetic analysis?
Good question. At low speeds (below a few hundred MHz), it's enough to just "drill a hole and plate it for conduction." But when you enter the GHz range, the situation changes completely. The via barrel (the copper-plated cylindrical part) has inductance, and capacitance forms between the pad and the plane. This parasitic LC creates impedance discontinuities.
What exactly does an impedance discontinuity do that's so bad?
If a 50Ω trace suddenly changes to 40Ω or 60Ω at the via, the signal reflects at that boundary. It's just like water splashing back when a thick water pipe suddenly narrows. The reflected signal returns to the transmitter, distorting the waveform and closing the eye pattern at the receiver. For DDR5 memory at 5.6Gbps (Nyquist frequency 2.8GHz) or PCIe 6.0 at 32GT/s (PAM4), managing the impedance of each individual via can determine the success or failure of the entire system.
What, a single via can have that much impact? There are hundreds of vias on a board, right?
Exactly. That's why in modern SI (Signal Integrity) design, all vias on critical nets are verified by extracting S-parameters using 3D FEM. Breaking down the via structure, we have these elements:
- Via Barrel: The copper-plated cylindrical hole. The main source of parasitic inductance.
- Pad: The land at the top and bottom of the via. The connection point to the trace.
- Antipad: The clearance hole in the plane layer that the via passes through. Determines capacitance.
- Stub: The unused remaining portion of the via barrel. The root cause of resonance.
- Barrel Wall: The copper plating thickness. Affects conductor loss and skin effect.
Via Impedance Theoretical Formulas
Are there formulas to calculate via impedance?
It can be approximated with a coaxial line model. Think of the via barrel as the inner conductor and the inner wall of the antipad as the outer conductor. First, the inductance:
$h$: Via barrel length [m], $d_{\text{anti}}$: Antipad outer diameter [m], $d_{\text{via}}$: Via barrel outer diameter [m]
What are typical values?
For example, with barrel length $h$ = 1.6 mm, via diameter $d_{\text{via}}$ = 0.3 mm, and antipad diameter $d_{\text{anti}}$ = 0.7 mm, the calculation gives $L_{\text{via}} \approx 270$ pH. The reactance at 10 GHz is $\omega L \approx 17\,\Omega$ — that's quite significant for a 50Ω line, right?
Next, the capacitance. The capacitance between the pad and the plane is:
$d_{\text{pad}}$: Pad outer diameter, $d_{\text{drill}}$: Drill hole diameter, $t$: Dielectric layer thickness, $\varepsilon_r$: Relative permittivity
From this parasitic LC, we can estimate the via's characteristic impedance:
Unit: [$\Omega$]. Typical values are around 25–45Ω, often lower than a 50Ω trace.
I see, so the via impedance isn't 50Ω, which causes reflection! If we increase the antipad diameter, does the impedance go up?
Exactly! But if you make the antipad too large, you create a big hole in the plane, forcing the return current to detour, and also worsen the power plane impedance. That's why we use FEM to find the optimal value.
Stub Resonance and Back-Drilling
I often hear that the via "stub" is a problem. What exactly happens?
This is the most serious via issue in high-speed design. For example, consider a 16-layer board where a signal transitions from L1 (surface) to L4 (inner layer 4). The via goes through L1 to L16, so the barrel portion from L4 to L16 is an unused "dead end" — this is the stub.
The stub behaves as an open-ended transmission line. Resonance occurs when the time for a signal to travel to the stub tip (open end) and reflect back matches the signal's half-wavelength. The resonance frequency is:
$c$: Speed of light ($3 \times 10^8$ m/s), $L_{\text{stub}}$: Stub length [m], $\varepsilon_{r,\text{eff}}$: Effective relative permittivity
Can you give me a concrete example? What happens with a 1.6mm board thickness and a 1.2mm stub?
Let's calculate for FR-4 ($\varepsilon_r \approx 4.0$). Assuming $\varepsilon_{r,\text{eff}} \approx 4.0$:
$f_{\text{stub}} = \frac{3 \times 10^8}{4 \times 1.2 \times 10^{-3} \times \sqrt{4.0}} = \frac{3 \times 10^8}{9.6 \times 10^{-3}} \approx 31.3\,\text{GHz}$
31 GHz — that might seem fine for PCIe 5.0 (16 GHz bandwidth), right? But in reality, the 3rd harmonic ($3f = 94$ GHz) also becomes problematic, and with lossy dielectrics, insertion loss gradually increases from much lower frequencies. Even for DDR5 at 5.6Gbps, a stub longer than 0.8mm can cause a notch of -3dB or more in S21, preventing the eye from opening.
Is "back-drilling" the solution to that?
Yes. Back-drilling is a process that physically removes the stub portion from the back side using a larger drill bit. Ideally, we want zero stub, but manufacturing tolerances leave a residual stub length, typically 100–200 μm (stub length tolerance ±50 μm). Even this residual stub resonates, but at a much higher frequency:
$L_{\text{stub}} = 150\,\mu\text{m}$ gives $f_{\text{stub}} = \frac{3 \times 10^8}{4 \times 150 \times 10^{-6} \times 2} = 250\,\text{GHz}$
250 GHz is not a problem for any current signal speed. That's why back-drill depth management is extremely important, and we use 3D FEM to parametrically sweep stub length and determine the allowable tolerance.
Antipad Design and Return Path
How do you decide the antipad size? You said earlier that "too big is also bad."
Sizing the antipad is a trade-off between SI (signal quality) and PI (power integrity):
| Antipad Diameter | SI (Signal Quality) | PI (Power Integrity) | Crosstalk |
|---|---|---|---|
| Small (Drill dia. +0.15mm) | △ Excessive capacitance, low Z | ○ Good plane continuity | ○ Low interference to adjacent vias |
| Medium (Drill dia. +0.25mm) | ○ Z ≈ 45-50Ω | ○ Acceptable range | ○ Good balance |
| Large (Drill dia. +0.40mm or more) | ○ Low capacitance, high Z | × Large hole in plane | × Increased coupling with adjacent vias |
In practice, we often use FEM analysis with antipad diameter as a parameter and adopt the minimum diameter where the via's S11 (reflection) is below -20 dB. There are also techniques using non-circular antipads (elliptical or stadium shapes) to control coupling in differential via pairs.
Physics of Return Path Discontinuity
What exactly happens with "return path discontinuity"? I hear that return current gets disrupted when changing layers with a via...
At high frequencies, return current takes the path of least impedance — it flows like a "shadow" on the ground plane right next to the signal. However, when the signal moves to another layer via a via, the return current's plane also needs to switch. If the two planes are the same net (e.g., both GND), they are connected by bypass capacitors or inter-plane capacitance. But if they are different nets (GND to VDD), the return current has nowhere to go.
Return current forced to take a detour creates a loop that acts like an antenna, emitting electromagnetic radiation (EMI). To evaluate this quantitatively, 3D FEM analysis including the placement of ground vias and plane configuration around the via is essential.
I see! That's why we place ground vias right next to signal vias?
Exactly. The best practice is to place a GND via within $\lambda/20$ (within 1.5mm at 10 GHz) of the signal via. For differential pairs, a "fence" structure with four GND vias placed on both sides of the two signal vias is commonly used.
The Story of How a "Just a Via" Caused a $100k Board Respinning
A server manufacturer once overlooked stub resonance in vias directly under a BGA when designing a DDR4-3200 board. Vias from L1 to L3 on an 8-layer board had a stub of 5 layers remaining, with a resonance frequency around 18 GHz. They thought even the 5th harmonic at 8 GHz was far from the DDR4-3200 data rate of 3.2 Gbps, but the broad insertion loss increase due to the stub's dielectric loss became a problem. Adding a back-drilling process increased the cost per production board by $2, resulting in huge additional costs for a lot of hundreds of thousands of boards. This was a mistake that could have been prevented by running 3D FEM just once during the design phase.
Via Equivalent Circuit Model (Detailed)
- Via barrel inductance $L_{\text{via}}$: Derived from the coaxial line model. Proportional to barrel length and the logarithm of the antipad/via diameter ratio. Typical value is 0.15–0.3 nH/mm. In the GHz range, $j\omega L$ becomes a series impedance of several ohms, which is not negligible for a 50Ω line.
- Pad-plane capacitance $C_{\text{pad}}$: Parallel plate capacitor determined by pad area and dielectric thickness. Exists for each plane layer, totaling around 50–200 fF. Larger capacitance lowers via impedance.
- Barrel resistance $R_{\text{via}}$: DC resistance is a few mΩ, but in the GHz range, the skin effect concentrates current to a skin depth of $\delta = \sqrt{2/(\omega\mu\sigma)}$, increasing effective resistance. For copper at 10 GHz, $\delta \approx 0.66\,\mu$m.
- Mutual inductance $M$: Mutual coupling between adjacent vias. In dense via arrays under BGAs, $M$ becomes a cause of crosstalk.
Theoretical Formula Application Limits
- Limits of coaxial model: The via barrel behaves as a perfect coaxial line only when the antipad is a uniform circle. In actual boards, antipad diameters differ per layer, requiring 3D FEM.
- Non-circular pads: Analytical formulas are not applicable for elliptical, oblong, or teardrop-shaped pads.
- Dielectric loss at high frequency: FR-4's $\tan\delta$ is frequency-dependent (e.g., Djordjevic-Sarkar model), making a single $\varepsilon_r$ value inaccurate.
- Skin effect: Above 10 GHz, copper barrel surface roughness (Rz) can exceed skin depth, requiring Hammerstad-Jensen correction or Huray roughness models.
Numerical Methods and Implementation
S-Parameter Extraction via 3D FEM
How exactly do you analyze a via? Do you mesh it and solve with FEM like structural analysis?
The basic flow is similar, but there are major differences from structural analysis. Electromagnetic field analysis solves Maxwell's equations. The most common method for 3D FEM analysis of vias is Frequency Domain FEM. It solves the following vector wave equation at each frequency point:
$k_0 = \omega/c$: Free space wavenumber, $\varepsilon_r^* = \varepsilon_r (1 - j\tan\delta)$: Complex relative permittivity
Unlike structural FEM which uses node-based shape functions, electromagnetic FEM uses edge elements (Nedelec elements). Edge elements automatically guarantee the continuity of the tangential component of the electric field and eliminate spurious modes (non-physical false eigenmodes) that occur with node elements.
How do you calculate S-parameters?
Set wave ports at the via's entrance and exit, then calculate S-parameters from the ratio of incident and reflected waves at each port. For a 2-port case:
- $S_{11}$ (Reflection): Reflection relative to the incident wave from port 1. Target is $|S_{11}| < -20$ dB.
- $S_{21}$ (Insertion Loss): Transmission from port 1 to 2. Target is $|S_{21}| > -1$ dB (loss within 1 dB).
- $S_{12}$, $S_{22}$: For symmetric structures, $S_{12} = S_{21}$, $S_{22} = S_{11}$.
For differential pairs, evaluate 4-port (or mixed-mode) S-parameters, assessing $S_{dd21}$ (differential insertion loss) and $S_{cd21}$ (mode conversion).
Meshing Strategy Around Vias
Meshing around vias seems tough. It's cylindrical, and the copper plating on the barrel is thin...
Via meshing is indeed challenging for CAE beginners. Let's organize the key points:
| Region | Recommended Mesh Size | Reason |
|---|---|---|
| Via barrel wall (copper) | $\leq \delta/3$ (1/3 of skin depth) | Resolve current concentration due to skin effect |
| Dielectric between antipad and pad | $\leq \lambda/20$ (1/20 wavelength at highest frequency) | Capture spatial variation of electric field |
| Barrel interior (air/resin fill) | $\leq$ Barrel diameter / 5 | Accuracy of internal electric field distribution |
| Plane layers (far field) | 3–5 times the via diameter | Reduce computational cost |
For solvers with adaptive mesh capability like HFSS, it's more efficient to set a coarse initial mesh and let the solver automatically refine it. The convergence criterion is typically $\Delta |S| < 0.01$ (change in S-parameter magnitude less than 1%). Usually, convergence is achieved in 3–5 adaptive passes.
Related Topics
なった
詳しく
報告