Eye Diagram Analysis

Good question. Let me explain the principle first. In digital communication, the transmitter sends out a sequence of "0" and "1" bits as a voltage waveform. The receiver samples this waveform to determine whether it's a "0" or a "1".

An eye diagram is created by cutting out the waveform for all possible bit patterns at each 1 UI (Unit Interval = time width of 1 bit) and overlaying them. This creates an opening in the center that looks like an "eye". The larger this opening, the easier it is for the receiver to correctly determine the bits.

With an ideal square wave, you would indeed get a rectangle. But real transmission paths have bandwidth limitations. High-frequency components are attenuated, causing the waveform's rise and fall times to slow down. Furthermore, the waveform changes slightly depending on the preceding and following bit patterns—this is ISI (Inter-Symbol Interference).

For example, in the patterns "0→1→1→1" and "0→1→0→1", the voltage level reached by the second "1" is different. In the former, it charges fully, but in the latter, it starts discharging immediately, so the voltage doesn't rise completely. When all such patterns are overlaid, the traces spread out, forming the "eye" shape.

Exactly. An open eye means there is margin for the receiver to correctly determine bits even in the presence of noise or timing variations. For PCIe Gen5 (32 GT/s), the post-equalization eye opening height must be at least 15 mV, and jitter must be below 3.5 ps. For Gen6 (64 GT/s, PAM4), the requirements are even stricter.

Of course. There are two fundamental metrics for eye diagrams.

Eye Height is the difference between the minimum voltage of the "1" level and the maximum voltage of the "0" level at the sampling timing:

$V_{\text{high,min}}$ is the minimum voltage of the "1" level across all bit patterns, and $V_{\text{low,max}}$ is the maximum voltage of the "0" level. The larger this value, the greater the noise margin. It indicates how much margin exists relative to the receiver buffer's threshold voltage.

Eye Width is the time difference between the left and right crossing points:

$T_{\text{UI}}$ is the time width of 1 UI, and $\text{Jitter}_{\text{pp}}$ is the peak-to-peak jitter of the crossing points. The larger this value, the greater the timing margin.

For example, for PCIe Gen5 (32 GT/s), $T_{\text{UI}} = 1/32 \times 10^9 \approx 31.25\,\text{ps}$. With 3.5 ps of jitter, the Eye Width is about 27.75 ps. This shows how much margin exists relative to the receiver CDR's lock range.

Exactly. In practice, a eye mask—a hexagonal prohibited area—is defined in the center of the eye, and it's verified that no waveform trace touches the mask. Both height and width must be satisfied simultaneously to pass the specification. The mask coordinates are specified in standards like USB4 and PCIe.

Jitter decomposition is essential for BER (Bit Error Rate) estimation. There are two main types of jitter:

• DJ (Deterministic Jitter): Bounded jitter with identifiable causes. Includes ISI, crosstalk, duty cycle distortion (DCD), periodic jitter (PJ), etc. Has an upper bound for its peak-to-peak value.
• RJ (Random Jitter): Jitter with a Gaussian distribution caused by thermal noise and shot noise. Theoretically has no upper bound.

Total Jitter (TJ) is estimated for a specific BER target using the following formula:

Here, $Q(\text{BER})$ is the inverse cumulative distribution function of the normal distribution (inverse of the Q-function). For BER = $10^{-12}$, $Q \approx 7.03$; for BER = $10^{-15}$, $Q \approx 7.94$.

Let's give a concrete example. Suppose a channel has $\text{DJ}_{\text{pp}} = 5\,\text{ps}$ and $\sigma_{\text{RJ}} = 0.3\,\text{ps}$. The TJ at BER = $10^{-12}$ is:

Yes. That's why reducing RJ is one of the most critical challenges in high-speed serial design. PLL jitter performance, power supply noise suppression, and board ground integrity directly affect RJ. While much of DJ can be compensated for by equalizers, RJ cannot.

The bathtub curve plots BER (vertical axis) against sampling phase (horizontal axis). As the name suggests, it resembles the cross-section of a bathtub. The left and right walls rise steeply, and there is a "bottom" in the center where BER is minimized.

Mathematically, the BER at sampling phase $\phi$ is derived from the convolution of the Gaussian distribution of RJ and the distribution of DJ. The one-sided BER (e.g., the left wall) is:

The right wall is calculated similarly, and the total BER is:

The "width of the bottom" of the bathtub is the timing margin for that BER target. For example, if the bottom width is 0.3 UI at BER = $10^{-12}$, then there is 0.3 UI of margin for the CDR's sampling phase. The PCI-SIG standard specifies this bottom width as "Minimum Eye Width at BER = $10^{-12}$".

Yes. An eye diagram is an overlay of waveforms, so it provides a "worst-case" view, but statistically it only contains information up to about BER $10^{-5}$. To evaluate BER at $10^{-12}$ or $10^{-15}$, jitter decomposition and the bathtub curve are essential.

The channel (transmission path) is characterized by S-parameters. For a 2-port network, the basic ones are insertion loss $S_{21}(f)$ and return loss $S_{11}(f)$. For differential pairs, $S_{dd21}$ (differential insertion loss) is used.

The time-domain pulse response $h(t)$ is obtained by the inverse Fourier transform of $S_{21}(f)$:

The received waveform $y(t)$ is the convolution of the transmitted waveform $x(t)$ and the channel impulse response:

In practice, S-parameters are either measured with instruments (VNA) or obtained through simulation with 3D electromagnetic solvers (HFSS, CST). It's common to cascade the S-parameters of PCB traces, connectors, vias, and packages to build an end-to-end channel characteristic.

Perfect understanding. For example, running a 10-inch differential pair on an FR-4 board can easily result in insertion loss exceeding -20 dB at the Nyquist frequency (16 GHz for PCIe Gen5). How to compensate for this loss is the core of equalizer design.

Good point. Time-domain bit-by-bit simulation is intuitive, but to directly verify BER = $10^{-12}$, you would need over $10^{13}$ bits, which is impractical.

That's where Statistical Eye Diagram Analysis comes in. This method analytically derives the probability distribution of ISI from the channel's pulse response, combines it with the convolution of RJ, and generates a BER map. The computational complexity is $O(2^N)$ (where $N$ is the number of cursors affecting ISI), but in practice, the effective number of cursors can be truncated to around 10-20, so it completes in seconds.

Sampling the channel's pulse response (SBR: Single Bit Response) yields cursor values $c_k$ at each UI. $c_0$ is the main cursor, $c_{-1}, c_{-2}, \ldots$ are pre-cursors, and $c_1, c_2, \ldots$ are post-cursors.

The sampled value of the received signal $y_n$ is:

$a_{n-k} \in \{-1, +1\}$ is the bit value. The part excluding the main cursor $c_0 \cdot a_n$ is ISI. Each ISI term takes one of two values, $\pm c_k$, with equal probability 1/2. Since all cursors are independent, the probability distribution of ISI is the convolution of the two-point distributions of each cursor.

If there are $N$ cursors, a discrete probability distribution is obtained from $2^N$ combinations. Convolving this with the Gaussian distribution of RJ yields the continuous probability density function of the sampled value, allowing calculation of the eye opening for any BER target.

Sharp. In fact, commercial tools (Keysight ADS, Ansys HFSS Transient, etc.) use fast algorithms based on characteristic functions (Fourier transform of the probability distribution). They multiply the characteristic functions of each cursor $\Phi_k(\omega) = \cos(c_k \omega)$, then use inverse FFT to convert back to the probability distribution. The computational complexity is $O(N \cdot M \log M)$ (where $M$ is the number of discretization points), which is orders of magnitude faster than enumerating all $2^N$ possibilities.