Transmission Line Theory and Signal Integrity Analysis

At low frequencies, a PCB trace is just a wire — current flows, voltage drops, done. But at GHz speeds — DDR5 memory at 6.4 Gbps, PCIe Gen 5 at 32 GT/s, 100G Ethernet SerDes — the trace behaves as a transmission line, and signal integrity is about making sure data arrives at the receiver correctly. The key issue is impedance mismatch: wherever the impedance changes — at vias, connectors, branch stubs, impedance-controlled layer transitions — part of the signal reflects back toward the source. That reflected energy causes ringing, intersymbol interference (ISI), and can flip bits. Transmission line theory gives you the tools to predict and prevent this.

The classic rule: transmission line effects become significant when the electrical length of the trace exceeds $\lambda/10$ at the highest frequency of interest (or equivalently, when the propagation delay exceeds the signal rise time divided by 6). For DDR5 signals with rise times of ~50 ps, the critical length is about 3–4 mm of PCB trace. A 10 cm trace — perfectly ordinary on a motherboard — is several wavelengths long at 10 GHz. At those lengths, lumped circuit models are completely wrong, and you must use distributed transmission line models or full 3D EM simulation.

Exactly the same physics. A signal on a trace propagates as a voltage wave at nearly the speed of light in the dielectric ($v_p = c/\sqrt{\varepsilon_{eff}} \approx 1.5 \times 10^8$ m/s on FR4). An abrupt impedance discontinuity is acoustically equivalent to a pipe with a sudden change in diameter — part of the energy bounces back. The ratio of reflected to incident amplitude is the reflection coefficient $\Gamma$. This is the fundamental mechanism behind crosstalk, ringing, and eye diagram degradation in high-speed designs.

Modeling the transmission line as a distributed RLCG circuit gives the telegrapher equations:

$R$ [Ω/m]: series resistance (frequency-dependent due to skin effect — at 10 GHz, current crowds into a thin surface layer), $L$ [H/m]: series inductance (governs wave propagation delay), $C$ [F/m]: shunt capacitance (depends on dielectric thickness and trace width), $G$ [S/m]: shunt conductance (dielectric loss — critical for FR4 above 5 GHz). These four parameters fully describe the electrical behavior of any transmission line geometry.

At DC, current flows uniformly across the conductor cross-section. As frequency rises, the skin effect confines current to an exponentially decaying layer near the surface:

For copper at 1 GHz, $\delta_s \approx 2.1$ μm; at 10 GHz, $\delta_s \approx 0.66$ μm. Since only this thin surface layer carries current, the effective resistance scales as $R \propto \sqrt{f}$. This is why insertion loss (dB/length) at high frequencies follows a characteristic $\sqrt{f}$ shape in a log-log plot, before dielectric loss ($G \propto f$) takes over at higher frequencies.

Characteristic impedance and propagation constant are derived from the telegrapher equations:

$\alpha$ [Np/m] is the attenuation constant and $\beta$ [rad/m] is the phase constant. For a microstrip, $Z_0$ depends on trace width $w$, dielectric height $h$, and relative permittivity $\varepsilon_r$. The phase velocity is $v_p = \omega/\beta$. The 50 Ω standard dates to 1930s US military conventions — a compromise between maximum power transfer (~30 Ω) and minimum loss (~77 Ω for air-filled coax). Consumer TV antennas use 75 Ω. Test and measurement equipment uses 50 Ω worldwide.

For a microstrip (trace on outer layer with ground plane below), the Hammerstad-Jensen formula gives:

$h$ = dielectric height, $w$ = trace width, $t$ = copper thickness. For standard FR4 ($\varepsilon_r = 4.2$, $h = 0.1$ mm, $t = 35$ μm): solving for 50 Ω gives $w \approx 0.19$ mm. Key rule: on a 4-layer board with 0.2 mm core, a trace width roughly equal to the dielectric thickness gives 50 Ω. For a stripline (trace buried between two ground planes), the impedance is lower for the same width because the dielectric completely surrounds the trace. Differential pair impedance (100 Ω differential = 50 Ω each) requires trace spacing to be designed simultaneously with trace width, using coupled-line field solver tools.

The reflection coefficient $\Gamma$ and the S-parameter $S_{11}$ are the standard metrics:

$Z_L$ is the load impedance. At $Z_L = Z_0$, $\Gamma = 0$ — perfect match, no reflection. Short circuit ($Z_L = 0$) gives $\Gamma = -1$; open circuit ($Z_L \to \infty$) gives $\Gamma = +1$. In digital design, the typical target is $|S_{11}| < -20\,\text{dB}$, meaning less than 1% of the power is reflected. The transmission coefficient $S_{21}$ measures the ratio of transmitted signal amplitude to the incident signal, and its magnitude $|S_{21}|$ in dB gives the channel insertion loss — a critical parameter for eye diagram quality.

TDR launches a fast-edge step signal onto the transmission line and measures the reflected waveform as a function of time. Since the propagation velocity is known, time maps directly to distance — so TDR creates a spatial impedance profile of the trace. Reflections appear as pulses in the TDR waveform: a positive pulse means the impedance increased at that point (open stub, via transition, narrow trace); a negative pulse means impedance decreased (pad, wider trace). TDR resolution is approximately $\delta_z = v_p \cdot t_r / 2$, where $t_r$ is the signal rise time. A 10 ps TDR can resolve features as small as 0.7 mm on FR4.

Crosstalk is electromagnetic coupling between adjacent traces — the aggressor signal induces a noise voltage on the victim trace through mutual inductance ($L_m$) and mutual capacitance ($C_m$). Two types exist:

• NEXT (Near-End CrossTalk): Noise at the same end as the source, propagating backward. Dominant mechanism: capacitive coupling. NEXT is especially harmful because it hits the receiver at the near end during the transmission window.
• FEXT (Far-End CrossTalk): Noise at the far end of the victim. Dominant mechanism: the difference between inductive and capacitive coupling. For stripline, inductive and capacitive coupling balance, giving very low FEXT — a key advantage of buried traces.

The crosstalk amplitude scales with trace spacing — reducing spacing from 3W (3× trace width) to 2W can double NEXT. Edge coupling (traces side by side) is worse than broadside coupling (traces stacked vertically). For critical differential pairs, maintain 3W spacing from adjacent single-ended signals.

Here are the most common problem areas in practice, in priority order:

1. Via discontinuities: Vias introduce parasitic inductance (the via barrel) and parasitic capacitance (antipad area). The net effect is typically an impedance spike followed by a dip. Via stub removal (back-drilling) eliminates the stub below the connection point and is essential for signals above ~10 GHz.
2. Connector transitions: Board-edge connectors disrupt the reference plane and change the cross-sectional geometry. 3D EM field solver analysis is needed for detailed characterization — 2D extraction significantly underestimates connector impedance peaking.
3. Reference plane changes: When a signal trace crosses a split in the reference plane (e.g., a power island), the return current must detour around the split. Stitch capacitors bridge power/ground splits to provide a low-impedance return path.
4. Differential pair length matching: Skew between the two traces of a diff pair generates common-mode noise from mode conversion. Target <100 ps skew using serpentine (accordion) routing. Match to within one grid step in the routing tool.
5. Simulation verification: Use SPICE or IBIS models to simulate time-domain waveforms. Check the eye diagram for mask compliance — an open eye means data is recoverable; a closed eye means bit errors are likely.

Back-drilling is a post-lamination drilling step that removes the unused portion of a via stub. For example, if a signal enters the board from the top, connects to layer 4 of a 10-layer stack, and the via barrel continues through to the bottom, the remaining 6 layers form a stub — essentially a short transmission line stub terminated in an open circuit. This stub creates a resonance at approximately $f_{res} = v_p/(4L_{stub})$. For a 1 mm stub on FR4, resonance is around 22 GHz — right in the 5G mmWave or USB4 Gen 3 band. Back-drilling removes the stub, eliminating the resonance entirely. The manufacturing surcharge (30–50% on PCB cost) is easily justified for 25 Gbps+ SerDes interfaces.

Here's a comparison of the major SI tools:

At 112 Gbps PAM4 (56 GBaud, Nyquist at 28 GHz), dielectric loss on FR4 is so severe that signals attenuate by 30–40 dB over a typical motherboard channel, leaving no margin for reliable reception. The engineering response involves multiple layers:

• Low-loss substrate materials: Megtron 6 ($\tan\delta \approx 0.004$), Rogers 4000 series — materials with flat $\varepsilon_r$ vs. frequency and much lower dissipation factor than FR4 ($\tan\delta \approx 0.020$). The PCB cost increase (3–5×) is justified for high-speed backplanes.
• Equalization: FFE (feed-forward equalization) at the transmitter pre-emphasizes high frequencies to compensate for frequency-dependent loss. DFE (decision-feedback equalization) at the receiver cancels ISI from the known transmitted history. Modern SerDes PHY chips combine up to 7-tap FFE + 20-tap DFE.
• FEC (Forward Error Correction): Coding like RS(544,514) recovers bit errors that slip through equalization, allowing operation at BER of $10^{-5}$ at the PHY while achieving $10^{-15}$ at the system level.
• 3D-IC packaging (HBM, UCIe): Short interconnects in chiplet architectures fundamentally reduce channel loss rather than compensating for it. UCIe (Universal Chiplet Interconnect Express) short-reaches operate below 5 mm, essentially eliminating insertion loss as a constraint.

A passive, reciprocal network must satisfy two mathematical constraints: passivity ($|S_{ij}| \le 1$ everywhere) and causality (no output before input). Real-world VNA measurements are corrupted by noise and calibration errors, which can cause small passivity violations — measured $|S_{11}|$ values slightly above 0 dB, or $|S_{21}|$ slightly above 0 dB at some frequencies. When you use such "passive-violated" S-parameters in a time-domain SPICE simulation, the model behaves as an active source — it generates energy from nothing — causing the simulation to diverge or oscillate. Most commercial SI tools include passivity enforcement algorithms (iterative convex optimization) that minimally perturb the S-parameters to restore passivity before import into simulation.

Start with a structured diagnostic flow:

1. TDR sweep: Launch a fast-edge TDR and look for impedance discontinuities along the trace. Any feature that shows up as a reflection is a candidate problem. Note the time position — convert to board distance using $z = v_p \cdot t/2$.
2. Check frequency-domain insertion loss: Plot $|S_{21}|$ vs. frequency. A drop of more than 3 dB at Nyquist usually means the eye will be marginal. If loss is gradual, it's the dielectric (substrate issue). If there are notches, it's resonances from stubs or reference plane transitions.
3. Isolate via stubs: Remove one via at a time in simulation and check if the notch disappears. Back-drilling is the fix.
4. Check crosstalk: Measure NEXT between adjacent traces using a VNA. If near-end noise is significant, increase trace separation or route on different layers.
5. Apply equalization: If the channel is fundamentally lossy (old FR4 substrate), enable FFE/DFE in the chip and re-check the eye margin.