Power Integrity and PDN Analysis

Power Integrity (PI) is a design technology for "delivering stable voltage to ICs." While Signal Integrity (SI) focuses on correctly transmitting the 0/1 bit stream, PI deals with the "quality of power" that drives those signals.

The problem is "instantaneous high current." For example, when a DDR5 memory controller starts simultaneous burst transfers, it suddenly draws several amperes of current in a few nanoseconds. The path from the VRM (Voltage Regulator Module) to the IC—called the PDN (Power Distribution Network)—has inductance, so a rapid current change $di/dt$ causes a voltage drop.

Good question. Let's consider DDR5's core voltage VDD = 1.1V. If the allowable ripple is ±3%, only 33mV of fluctuation is allowed. Even a 10mm trace on a board has several nH of inductance. With a 2A/ns current change, $V = 2 \times 10^{-9} \times 2 \times 10^9 = 4$V drop "would normally" occur. Of course, decoupling capacitors prevent it from getting that bad, but if the design is flawed, exceeding 33mV is easy.

The starting point for PDN design is calculating the Target Impedance. This is the upper limit value where, if the PDN impedance seen from the IC's power pin is "below this value," the voltage ripple stays within the allowable range.

Yes, it becomes:

$$Z_{\text{target}} = \frac{1.1 \times 0.03}{2} = 16.5\,\text{m}\Omega$$

This means the PDN impedance must be kept below 16.5mΩ from DC up to the upper limit of the target frequency band. This requirement of "below a constant value across the entire frequency band" is the difficulty of PDN design. Low frequencies are handled by the VRM, mid-frequencies by bulk capacitors, high frequencies by MLCCs (Multi-Layer Ceramic Capacitors), and ultra-high frequencies by on-die capacitors.

Exactly. VRM → bulk caps → MLCCs → on-die caps, each "passes the baton" at their respective frequency bands. The designer's skill is in ensuring the impedance doesn't exceed the target at the baton-pass boundaries (anti-resonance points).

PDN impedance is expressed as a function of frequency $Z_{\text{PDN}}(f)$. Its relationship with voltage ripple is:

Looking at a typical PDN impedance profile:

• ~1kHz and below: Dominated by VRM output impedance. Kept low by control loop gain.
• 1kHz～1MHz: Bulk capacitors (electrolytic capacitors) supply charge.
• 1MHz～100MHz: MLCCs take the lead. Impedance rises due to ESL (Equivalent Series Inductance).
• 100MHz～1GHz: Dominated by power plane parallel-plate capacitance and on-die capacitance.

When two capacitors are connected in parallel, there is a frequency band where one is capacitive (impedance falling) and the other is inductive (impedance rising). There, parallel resonance (anti-resonance) occurs, creating a sharp impedance peak. Expressed mathematically, the anti-resonance frequency for two capacitors $C_1$, $C_2$ (each with ESL $L_1$, $L_2$) is:

$$f_{\text{anti}} = \frac{1}{2\pi\sqrt{L_1 \cdot \frac{C_1 \cdot C_2}{C_1 + C_2}}}$$

If this anti-resonance peak exceeds the target impedance, voltage ripple increases at that frequency.

In PDN design, we need to think in terms of actual equivalent circuits, not "ideal capacitors." A single MLCC is represented by an RLC model like this:

There are three important parameters here:

• C (Capacitance): Charge supply capability at low frequencies. Larger values are effective down to lower frequencies.
• ESR (Equivalent Series Resistance): Determines the lower limit of impedance at the self-resonant frequency. Typically a few mΩ to tens of mΩ.
• ESL (Equivalent Series Inductance): The culprit that increases impedance in the high-frequency region. Includes inductance from MLCC mounting pads, vias, and traces.

The self-resonant frequency (SRF) is $f_{\text{SRF}} = \frac{1}{2\pi\sqrt{\text{ESL} \cdot C}}$, where the impedance is minimum (= ESR).

For an 0402 size MLCC with ESL ≈ 0.5nH, C = 100nF (0.1μF):

$$f_{\text{SRF}} = \frac{1}{2\pi\sqrt{0.5 \times 10^{-9} \times 100 \times 10^{-9}}} \approx 22.5\,\text{MHz}$$

This means above 22.5MHz, this capacitor does not function as a "capacitor" but behaves as an inductor. So to lower impedance on the high-frequency side, capacitors with smaller capacitance and lower ESL are needed.

The power plane and ground plane form a parallel-plate structure separated by a thin dielectric. This can be viewed as a resonator with distributed capacitance and inductance. The resonant frequency for a rectangular plane (size $a \times b$, dielectric thickness $d$, relative permittivity $\varepsilon_r$) is:

Here $m$, $n$ are mode indices (0, 1, 2, ...), and $c$ is the speed of light. For example, for a 100mm × 80mm board with $\varepsilon_r = 4.2$ (FR-4), the (1,0) mode resonant frequency is:

$$f_{10} = \frac{3 \times 10^8}{2\sqrt{4.2}} \times \frac{1}{0.1} \approx 732\,\text{MHz}$$

A sharp peak appears in the PDN impedance at this frequency. Using FEM, we can visualize the voltage distribution of this resonant mode.

We can see the positions of the resonant mode's "antinodes" and "nodes." If an IC is located at an antinode, voltage fluctuation is maximized, so placing decoupling capacitors at those antinode positions can effectively suppress resonance. Conversely, placing capacitors at node positions has little effect. This is the basic idea behind FEM-based placement optimization.

The simplest is the lumped-parameter equivalent circuit model. The VRM, bulk caps, MLCCs, vias, and planes are each represented by RLC circuits and solved as a connected network.

The PDN impedance for $n$ decoupling capacitors connected in parallel is:

$$Z_{\text{PDN}}(f) = \left(\sum_{i=1}^{n} \frac{1}{Z_{\text{cap},i}(f)}\right)^{-1} \parallel Z_{\text{plane}}(f) \parallel Z_{\text{VRM}}(f)$$

Here, each capacitor's impedance is:

$$Z_{\text{cap},i}(f) = \text{ESR}_i + j2\pi f \cdot \text{ESL}_i + \frac{1}{j2\pi f \cdot C_i}$$

Yes, lumped-parameter models can be calculated sufficiently with Excel or Python. However, there are limitations. The distributed effects of power planes (position dependency, resonant modes) cannot be captured by lumped-parameter models. Problems where results change based on "where capacitors are placed on the plane" need to be solved with FEM or the Method of Moments (MoM).

Power plane FEM analysis often uses the Cavity Model. It treats the thin dielectric layer between the power and ground planes in a 2D manner, solving the 2D Helmholtz equation derived from Maxwell's equations:

Here $V$ is the inter-plane voltage, $k = \omega\sqrt{\mu_0 \varepsilon_0 \varepsilon_r}$ is the wavenumber, $J_z$ is the current density flowing between the planes, and $d$ is the dielectric thickness. Discretizing this equation with FEM gives:

$$([K] - k^2[M])\{V\} = \{F\}$$

$[K]$ is the stiffness matrix (discretization of $\nabla^2$), $[M]$ is the mass matrix, and $\{F\}$ is the current source vector.

Sharp observation. Setting $\{F\} = 0$ gives the eigenvalue problem $[K]\{V\} = k^2[M]\{V\}$, yielding resonant modes and frequencies. It has exactly the same mathematical structure as structural natural frequency analysis. The plane is meshed with 2D triangular or quadrilateral elements, and decoupling capacitors are connected as RLC lumped parameters at port locations.

Yes, a frequency sweep. For each frequency $f$, update $k = 2\pi f\sqrt{\mu_0\varepsilon_0\varepsilon_r(1-j\tan\delta)}$ and solve the system of equations. Here $\tan\delta$ is the dielectric loss tangent, which determines the resonance peak height (Q factor). For FR-4, $\tan\delta \approx 0.02$.

Applying a 1A current at the IC's power pin location and calculating the voltage at the same point gives the PDN impedance at that point:

$$Z_{\text{PDN}}(f) = \frac{V_{\text{port}}(f)}{I_{\text{port}}(f)}$$