PCB Layout EMC Analysis

Category: Electromagnetic Analysis – EMC | Revised 2026-10-01
CAE visualization for pcb emc layout theory - technical simulation diagram
PCB Layout EMC Analysis

Theory: loops and cables are antennas

Overview

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What matters most in layout to reduce a board's radiated noise?

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There are two main sources. One is the loop formed by signal and return current, radiating like a small loop antenna (differential-mode radiation). The other is current on attached cables that isn't cancelled by its return, making long cables radiate like rod antennas (common-mode radiation). Differential mode scales with area, so the basic rule is an unbroken ground plane so return current flows directly beneath each trace. Common mode matters even at tiny currents, so layout that avoids ground potential differences and measures at cable exits are key. Let's compare their size with simple formulas.

Differential- and common-mode radiation

$$ E_{DM} = 1.316\times10^{-14}\,\frac{f^2 A\,I_{DM}}{r}\ \mathrm{[V/m]},\qquad E_{CM} = 1.257\times10^{-6}\,\frac{f\,L\,I_{CM}}{r}\ \mathrm{[V/m]} $$

f is frequency (Hz), A loop area (m²), L cable length (m) and r distance (m). Both are small-antenna approximations (after Ott) without ground reflection. The comparison limit is FCC Class B (residential, 3 m): 150 μV/m (43.5 dBμV/m) for 88–216 MHz.

Coffee Break Trivia

Where does return current flow?

At low frequency, return current takes the path of least resistance — the shortest route through the ground plane. At high frequency it takes the path of least inductance, directly beneath the signal trace, which is also the path of minimum loop area. This became a central concern in 1990s high-speed digital board design, leading to basic layout rules such as "don't split the ground plane" and "don't route signals across plane gaps".

Worked examples

Example 1: loop area and emission (100 MHz, 20 mA, 3 m)

Loop areaFielddBμV/mMargin to Class B
10 cm² (detour around gap)877 μV/m58.9−15.3 dB
1 cm²87.7 μV/m38.9+4.7 dB
0.1 cm² (over plane, 50 mm × 0.2 mm)8.8 μV/m18.9+24.7 dB

Example 2: common-mode current on a 1 m cable (100 MHz, 3 m)

Common-mode currentFielddBμV/m
1 μA42 μV/m32.4
3.6 μA150 μV/m (limit)43.5
5 μA210 μV/m46.4
20 μA838 μV/m58.5
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The board loop carries 20 mA, yet a few microamps on the cable radiate as much.

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In differential mode, outgoing and return currents flow close together in opposite directions and largely cancel; only the small residual radiates, so emission scales with area and stays small for a small loop even at large current. Common-mode current has nothing to cancel it, so the whole 1 m cable radiates efficiently. Here 5 μA of common-mode current radiated more than twice as much as the 20 mA, 1 cm² loop. Much common-mode current arises from small voltage drops that return current creates across the ground plane, so an unbroken plane helps both modes. Then filters or ferrite cores at cable exits reduce current on the cable.

Layout and analysis workflow

  1. Place an unbroken ground plane immediately adjacent to high-speed signal layers.
  2. Route so signals never cross ground-plane gaps.
  3. Keep strong signals such as clocks short and away from board edges and connectors.
  4. Put filters or common-mode chokes at cable exits and bond ground to the chassis at one point.
  5. Locate strong sources with field simulation and near-field probes.
Coffee Break Trivia

“One trace cost 10 dB”

A product failed radiated-emission testing near 100 MHz. On the board, a clock trace crossed a gap in a ground plane split for power reasons. Return current detoured around the gap, enlarging the loop, and the voltage difference across the gap drove common-mode current onto the cable. Rerouting so the trace no longer crossed the gap cut emission at that frequency by more than 10 dB, within the limit.

Common mistakes

Mistakes and fixes

MistakeEffectFix
Splitting the ground planeLoop area growsDon't cross gaps
Only addressing differential modeCable emission remainsSuppress common mode
Clocks near board edgesEdge radiationInner layers, centre
No measures at cable exitsCM current escapesFilters, ferrites
Evaluating just before testCostly reworkAnalyse during design
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Coupled AnalysisStructural AnalysisThermal Analysis
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