Gate Driver Circuit Design
Theory: the gate is a capacitor; think in charge
Overview
After switching to SiC MOSFETs I no longer know how to choose gate resistance.
A MOSFET gate is a capacitor, so switching means moving a fixed amount of charge in and out. Gate resistance sets that current and hence switching speed. Faster switching cuts losses, but SiC changes voltage very quickly (tens of V/ns), and that change drives current through device capacitance into the opposite device's gate. With large gate resistance that current lifts the gate voltage and a device meant to be off turns on. So separate on and off resistances are used, or negative voltage is applied when off. Let's check numerically.
Drive power, peak current and Miller period
Assumed device: gate charge Qg 60 nC, Miller charge Qgd 20 nC, input capacitance Ciss 2 nF, reverse transfer capacitance Crss 10 pF, Miller plateau 7 V, threshold 2.5 V (about 1.8 V at 150 °C), internal gate resistance 3 Ω.
Gate voltage lift from dv/dt
Current Crss·dv/dt flows through the off device's reverse transfer capacitance and becomes voltage across the gate resistance; smoothing by gate capacitance is approximated by time constant τ. Gate-loop inductance is ignored.
The trouble with switches that are too fast
In the silicon IGBT era, switching ran at a few V/ns and many designs turned gates off at 0 V. When SiC and GaN MOSFETs reached practice in the 2010s, voltage slew rose to tens of V/ns; losses fell sharply but false turn-on and noise became prominent. SiC MOSFETs have relatively low thresholds that drop further with temperature, so negative bias and Miller clamps became standard gate-drive techniques.
Worked examples
Example 1: external gate resistance and drive speed
| External Rg | Total | Peak current (22 V) | Turn-on Miller period | Turn-off (−4 V) | Turn-off (0 V) |
|---|---|---|---|---|---|
| 2 Ω | 5 Ω | 4.40 A | 9.1 ns | 9.1 ns | 14.3 ns |
| 5 Ω | 8 Ω | 2.75 A | 14.5 ns | 14.5 ns | 22.9 ns |
| 10 Ω | 13 Ω | 1.69 A | 23.6 ns | 23.6 ns | 37.1 ns |
Drive power at 200 kHz is 216 mW for +18/0 V and 264 mW for +18/−4 V (54 and 66 mW at 50 kHz).
Example 2: gate lift when switching 800 V
| dv/dt | Off-side external Rg | Lift | Peak with 0 V off | Peak with −4 V off |
|---|---|---|---|---|
| 20 V/ns | 2 Ω | 0.98 V | 0.98 V | −3.02 V |
| 20 V/ns | 10 Ω | 2.04 V | 2.04 V | −1.96 V |
| 50 V/ns | 0.5 Ω | 1.57 V | 1.57 V | −2.43 V |
| 50 V/ns | 5 Ω | 2.53 V | 2.53 V | −1.47 V |
| 50 V/ns | 10 Ω | 2.99 V | 2.99 V | −1.01 V |
At 50 V/ns, even 0.5 Ω external resistance with 0 V off reaches 1.57 V, close to threshold.
The 3 Ω internal gate resistance can't be reduced externally, so lowering the external resistor has limits. At high temperature the threshold drops to about 1.8 V, and gate-loop inductance adds ringing in practice, so 0 V turn-off leaves little margin. Turning off at about −4 V keeps the lift at −1.5 V. Another approach is a Miller clamp, which ties gate to source through low impedance while off, diverting the injected current. SiC gates tolerate negative voltage poorly, though, with datasheets often limiting it to around −5 V, so don't bias too deep. Separate on and off resistances also preserve turn-on speed while suppressing false turn-on.
Design workflow
- Read Qg, Qgd, Crss, threshold vs temperature and gate-voltage limits from the datasheet.
- Choose driver IC and isolated supply from drive power and peak current.
- Compute false-turn-on margin at maximum dv/dt and decide on negative bias or Miller clamp.
- Minimise the gate loop and use a Kelvin source connection.
- Measure waveforms with a double-pulse test and compare with calculation.
“An inverter that failed only when hot”
A SiC inverter ran fine at room temperature but failed mid-way through a high-temperature endurance test when upper and lower devices turned on together. Gates were turned off at 0 V. At room temperature the threshold, about 2.5 V, withstood the dv/dt-induced lift, but at 150 °C it fell to about 1.8 V and the lift exceeded it. Switching to −4 V negative bias and smaller off-side gate resistance stopped false turn-on even when hot.
Common mistakes
Mistakes and fixes
| Mistake | Effect | Fix |
|---|---|---|
| Designing at room-temperature threshold | False turn-on when hot | Check at hot values |
| Same resistance on and off | Can't balance speed and safety | Separate resistors |
| Too deep negative bias | Gate degradation | Stay within rating |
| Large gate loop | Ringing, false turn-on | Kelvin connection |
| Forgetting internal Rg | Speed overestimated | Use total Rg |
I'd like to learn related topics.
Related pages include parasitic inductance, EMI from switching, wide-bandgap device simulation, power device thermal design and power module packaging.
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