Compact Thermal Model (Delphi/JEDEC)
Idea: representing a part with a few nodes
Overview
In a whole-board thermal analysis, modelling dozens of ICs in detail makes the run never finish.
That's what compact thermal models are for. Instead of meshing the die, bond wires, lead frame and mould compound, you replace the part with a box whose junction connects to a few surface points through thermal resistances. The underlying compromise: however simple, it's fine as long as the junction temperature is right under the cooling conditions you'll use. How simple you can go depends on how the part is cooled.
Common model types
| Model | Nodes | Characteristics |
|---|---|---|
| Single resistance (θJA) | Junction and ambient | Valid only on the test board; unsuitable for system analysis |
| Two-resistor (JEDEC) | Junction, top, board | Built from datasheet RJC and RJB; error depends on cooling |
| DELPHI (multi-node) | Top, bottom and sides split into several nodes | Resistances fitted to a detailed model over many cooling conditions; robust to changing boundary conditions |
Two-resistor model equation
$R_{top}$ is the resistance from the top to ambient (heat sink or convection) and $R_{board}$ from the board surface to ambient. Representing the whole top and the whole board face by one temperature each is where the model's limits lie.
Born from a European research collaboration
DELPHI was the name of a European collaborative research project in the early 1990s involving electronics manufacturers and analysis-software companies. The aim was a thermal model of a component that equipment makers could use for accurate analysis without the part supplier revealing its internals. It produced a method of fitting a resistor network to a detailed model over many cooling conditions, and the idea of a boundary-condition-independent model was later adopted in JEDEC standards. Its great advantage is passing on thermal behaviour while keeping the internal design confidential.
Worked example: how error changes with cooling
The reference “detailed” model
Take as the “detailed” model a four-node network — junction, top centre, top periphery and bottom — with junction–top centre 8 K/W, junction–top periphery 30 K/W, top centre–periphery 6 K/W and junction–bottom 4 K/W. The two-resistor model derived from it gives $R_{JC} = 6.32$ K/W (whole top cooled) and $R_{JB} = 4.00$ K/W (board only). The two were compared under various cooling conditions (junction rise per watt):
| Cooling condition | Detailed | Two-resistor | Error |
|---|---|---|---|
| Cold plate on the whole top | 6.32 K/W | 6.32 K/W | 0 % |
| Board only | 4.00 K/W | 4.00 K/W | 0 % |
| Small heat sink on top centre + board | 5.42 K/W | 5.31 K/W | −2.1 % |
| Natural convection on top + good board | 10.14 K/W | 10.11 K/W | −0.3 % |
| Spreader touching the periphery only | 8.31 K/W | 6.26 K/W | −24.6 % |
Cooling only from the periphery reads 25% low — and on the unsafe side.
The two-resistor model treats the top as one temperature, so it can't tell where on the top the heat leaves. The centre above the junction is the easier path, and when heat can only escape through the periphery that difference matters. A multi-node model that separates the top centre and periphery — here the detailed model itself — has zero error in every case. That is the DELPHI idea.
Use in system-level analysis
Choosing a model
- Low-power parts or those with ample temperature margin are often fine with a two-resistor model.
- For parts with small margins, or where a heat sink or spreader touches only part of the package, use a DELPHI or detailed model.
- Check the format supplied by the manufacturer (two-resistor, DELPHI, detailed) and the cooling conditions it was validated under.
Verification procedure
- For critical parts, compare against a detailed model (or manufacturer's detailed data) under cooling close to actual use.
- If the error in junction rise is within a few percent, use the compact model in the system analysis.
- On hardware, estimate junction temperature from the case-top temperature and ψJT and compare with the analysis.
Where the compact model's faces go
A common problem when placing compact models in CFD is that the model's outer faces aren't properly connected to the board or enclosure — the top node isn't in face contact with the heat sink, or the bottom node isn't thermally connected to the board's copper layers. Even with correct resistances, the heat exits are then blocked. After placing a model, output the heat leaving each node and confirm it flows along the intended paths.
Common mistakes
Mistakes and fixes
| Mistake | Effect | Fix |
|---|---|---|
| Representing a part by θJA alone | Temperatures badly wrong on the real board | Use at least a two-resistor model |
| Two-resistor model under partial cooling | Junction temperature wrong on the unsafe side | Use DELPHI or a detailed model |
| No contact between model faces and board | Heat exits blocked | Output heat per node and check |
| Not checking validation conditions | Used outside its valid range | Check the supplier's validation conditions |
I'd like to try building up the resistances myself.
Use the LED junction temperature simulator to build the chain from part to ambient and the heat sink design calculator for the heat-sink side. The basic relations are in thermal resistance (Rth) models, the overall workflow in junction temperature prediction and board-level thermal analysis, and heat flow into the board in thermal vias.