A method that launches a fast-rising voltage step into an interconnect and measures returning reflections versus time. Reflections arise where impedance changes; return time gives location and amplitude gives the impedance change. It is used to qualify PCB traces, connectors and cables.

What sets TDR resolution?

Mainly the step rise time. The distinguishable distance is roughly propagation speed × rise time ÷ 2 — about 2.9 mm at 35 ps and 8.3 mm at 100 ps for an FR-4 microstrip. Shorter discontinuities blur into smaller-looking changes.

How do short discontinuities like vias appear?

Short discontinuities such as parasitic capacitance show as a momentary impedance dip whose depth is inversely proportional to rise time. A 0.3 pF via looked like 32 Ω at 35 ps rise time but 43 Ω at 100 ps. Unless evaluated at the actual signal's rise time, the effect is over- or underestimated.

PCB Signal Integrity Evaluation Using TDR Analysis

Category: Electromagnetics – Signal Integrity | Revised 2026-10-01

TDR waveform showing PCB trace impedance profile. Via and connector discontinuities are visualized as reflections in the step response.

Theory: reading impedance from reflections

Overview

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On a high-speed board, the via impedance from TDR measurement and simulation disagree. Is one of them wrong?

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Both may be right. TDR launches a fast step and views reflections from impedance changes in time. For long traces, impedance reads directly from reflection amplitude. But short discontinuities like vias, passed within the step's rise, blur with rise time — so the same via looks like different impedances on TDRs with different rise times. When comparing, match the rise times of measurement and simulation.

Reflection coefficient and resolution

$$ \Gamma = \frac{Z_2 - Z_1}{Z_2 + Z_1}, \qquad Z(t) = Z_0\,\frac{1 + \rho(t)}{1 - \rho(t)}, \qquad \Delta x \approx \frac{v\,t_r}{2},\ \ v = \frac{c}{\sqrt{\varepsilon_{eff}}} $$

$\Gamma$ is the reflection coefficient where impedance changes from $Z_1$ to $Z_2$, $\rho(t)$ the reflected fraction measured by TDR, $t_r$ step rise time and $\varepsilon_{eff}$ effective permittivity.

Short capacitive discontinuity

$$ \rho_{min} \approx -\frac{Z_0\,C}{2\,t_r} \quad (t_r \gg Z_0 C/2) $$

The reflection depth from a shunt parasitic capacitance $C$ is inversely proportional to rise time; the faster the rise, the deeper the same via's dip appears.

Coffee Break Trivia

From cable fault-finding to circuit boards

Using reflections to locate faults on transmission lines goes back to fault-finding on telegraph and telephone cables. After the Second World War, as radar technology matured, instruments timing reflections of fast pulses were built, and by the 1960s TDR combined with sampling oscilloscopes became practical. As digital circuits sped up and board traces themselves behaved as transmission lines, TDR became indispensable for board impedance control. Today the same waveform is computed by electromagnetic simulation and compared with measurement.

Worked examples

Example 1: microstrip lines

FR-4 (relative permittivity 4.3), 0.2 mm dielectric, using simple formulas neglecting copper thickness:

Trace width	Impedance	Effective εr	Speed
0.20 mm	71.5 Ω	3.11	1.70×10⁸ m/s
0.35 mm	53.5 Ω	3.24	1.67×10⁸ m/s
0.50 mm	42.9 Ω	3.34	1.64×10⁸ m/s

If a 0.35 mm trace narrows to 0.2 mm, the reflection coefficient is 0.145. Resolution is about 2.9 mm at 35 ps rise time and 8.3 mm at 100 ps.

Example 2: how a 0.3 pF via appears

Rise time	Min reflection (formula)	Min reflection (time-domain)	Apparent impedance
35 ps	−0.214	−0.212	32.5 Ω
100 ps	−0.075	−0.075	43.0 Ω

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The same via looks like 32 Ω or 43 Ω. Which is real?

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Better to think a via has no single impedance. It's too short; its defining property is 0.3 pF of parasitic capacitance. The dip TDR shows is set by that capacitance together with rise time. What matters is how much reflection the actual signal's rise time produces. If the signal rises in 100 ps, there's no need to panic at the 32 Ω seen on a 35 ps TDR. When comparing simulation with measurement, filter the simulation to the same rise time.

Evaluation workflow

Compute trace impedance from the stack-up (thicknesses, permittivity, copper thickness).
Obtain S-parameters by 3D electromagnetic analysis including vias, connectors and pads.
Compute TDR waveforms from the S-parameters at the actual signal rise time.
Compare with prototype TDR at the same rise time.
Check large reflections in eye diagrams too, revising geometry or stack-up.

Coffee Break Trivia

“Everything 5 Ω high after fabrication”

A board designed for 50 Ω measured about 55 Ω on every trace by TDR. Investigation found etching had made traces narrower than designed, with trapezoidal cross-sections, and the laminate's permittivity at high frequency was a little lower than the catalogue's 1 MHz value. Recomputing with actual width, trapezoidal section and frequency-appropriate permittivity matched the measurement well. Impedance calculations need post-fabrication geometry and material data, not just design dimensions.

Common mistakes

Mistakes and fixes

Mistake	Effect	Fix
Comparing at different rise times	Apparent mismatch	Filter to the same rise time
Reading short features literally	Over- or underestimation	Evaluate as C or L
Using design dimensions	Mismatch after fabrication	Actual cross-section
Permittivity at 1 MHz	Error at high frequency	Frequency-dependent values
Ignoring multiple reflections	Later discontinuities misread	Peel reflections layer by layer

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I'd like to try related calculations.

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Try the reflection coefficient calculator and differential pair impedance calculator. Related pages include transmission lines, impedance matching, via modelling, S-parameters and eye diagrams.

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